
85
32142D–06/2013
ATUC64/128/256L3/4U
8.6
Functional Description
8.6.1
USB General Operation
8.6.1.1
Initialization
After a hardware reset, the USBC is in the Reset state. In this state:
The module is disabled. The USBC Enable bit in the General Control register
(USBCON.USBE) is reset.
The module clock is stopped in order to minimize power consumption. The Freeze USB Clock
bit in USBCON (USBCON.FRZCLK) is set.
The USB pad is in suspend mode.
The internal states and registers of the device are reset.
The Freeze USB Clock (FRZCLK), USBC Enable (USBE), in USBCON and the Low-Speed
mode bit in the Device General Control register (UDCON.LS) can be written to by software,
so that the user can configure pads and speed before enabling the module. These values are
only taken into account once the module has been enabled and unfrozen.
After writing a one to USBCON.USBE, the USBC enters device mode in idle state.
Refer to
Section 8.6.2 for the basic operation of the device mode.
The USBC can be disabled at any time by writing a zero to USBCON.USBE, this acts as a hard-
ware reset, except that the FRZCLK,bit in USBCON, and the LS bits in UDCON are not reset.
8.6.1.2
Interrupts
One interrupt vector is assigned to the USBC.
8.6.1.3
Frozen clock
When the USB clock is frozen, it is still possible to access the following bits: FRZCLK, and USBE
in the USBCON register, and LS in the UDCON register.
When FRZCLK is set, only the asynchronous interrupt can trigger a USB interrupt (see
Section8.6.1.4
Speed control
Device mode
When the USBC interface is in device mode, the speed selection is done by the UDCON.LS bit,
connecting an internal pull-up resistor to either DP (full-speed mode) or DM (low-speed mode).
The LS bit shall be written before attaching the device, which can be simulated by clearing the
UDCON.DETACH bit.