參數(shù)資料
型號(hào)： MR80C32E-16P883
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 16 MHz, MICROCONTROLLER, CQCC44
文件頁數(shù)： 101/176頁
文件大?。?/td> 2962K
代理商： MR80C32E-16P883
30
2535J–AVR–08/10
ATtiny13
7. Power Management and Sleep Modes
The high performance and industry leading code efficiency makes the AVR microcontrollers an
ideal choise for low power applications. In addition, sleep modes enable the application to shut
down unused modules in the MCU, thereby saving power. The AVR provides various sleep
modes allowing the user to tailor the power consumption to the application’s requirements.
7.1
Sleep Modes
Figure 6-1 on page 23 presents the different clock systems in the ATtiny13, and their distribu-
tion. The figure is helpful in selecting an appropriate sleep mode. Table 7-1 shows the different
sleep modes and their wake up sources.
Note:
1. For INT0, only level interrupt.
To enter any of the three sleep modes, the SE bit in MCUCR must be written to logic one and a
SLEEP instruction must be executed. The SM1..0 bits in the MCUCR Register select which
sleep mode (Idle, ADC Noise Reduction, or Power-down) will be activated by the SLEEP instruc-
tion. See Table 7-2 on page 33 for a summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU
is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the Register File and
SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,
the MCU wakes up and executes from the Reset Vector.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed
level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 45
for details.
7.1.1
Idle Mode
When the SM[1:0] bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode,
stopping the CPU but allowing Analog Comparator, ADC, Timer/Counter, Watchdog, and the
interrupt system to continue operating. This sleep mode basically halts clkCPU and clkFLASH, while
allowing the other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required,
the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator
Table 7-1.
Active Clock Domains and Wake-up Sources in the Different Sleep Modes
Active Clock Domains
Oscillators
Wake-up Sources
Sleep Mode
clk
CPU
clk
FL
AS
H
clk
IO
clk
ADC
Mai
nClock
So
urce
Enabl
ed
INT0
and
Pi
nC
han
ge
SPM/
EEPROM
R
eady
ADC
Other
I/O
W
a
tchd
og
Interrupt
Idle
X
ADC Noise
Reduction
XX
XX
X
Power-down
X
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