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參數(shù)資料
| 型號： | MR80C32E-16P883 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 16 MHz, MICROCONTROLLER, CQCC44 |
| 文件頁數(shù)： | 154/176頁 |
| 文件大?。?/td> | 2962K |
| 代理商： | MR80C32E-16P883 |
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79
2535J–AVR–08/10
ATtiny13
13.2 Register Description
13.2.1
ADCSRB – ADC Control and Status Register
Bit 6 – ACME: Analog Comparator Multiplexer Enable
When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the
ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written
logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed
description of this bit, see “Analog Comparator Multiplexed Input” on page 78.
13.2.2
ACSR– Analog Comparator Control and Status Register
Bit 7 – ACD: Analog Comparator Disable
When this bit is written logic one, the power to the Analog Comparator is switched off. This bit
can be set at any time to turn off the Analog Comparator. This will reduce power consumption in
Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be
disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is
changed.
Bit 6 – ACBG: Analog Comparator Bandgap Select
When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog
Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Compar-
ator. When the bandgap reference is used as input to the Analog Comparator, it will take certain
time for the voltage to stabilize. If not stabilized, the first value may give a wrong value.
Bit 5 – ACO: Analog Comparator Output
The output of the Analog Comparator is synchronized and then directly connected to ACO. The
synchronization introduces a delay of 1 - 2 clock cycles.
Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode defined
by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set
and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding inter-
rupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Com-
parator interrupt is activated. When written logic zero, the interrupt is disabled.
Bit 2 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny13 and will always read as zero.
Bit
7
654
3210
–
ACME
–
ADTS2
ADTS1
ADTS0
ADCSRB
Read/Write
R
R/W
R
R/W
Initial Value
0
000
0000
Bit
765
4321
0
ACD
ACBG
ACO
ACI
ACIE
–
ACIS1
ACIS0
ACSR
Read/Write
R/W
R
R/W
R
R/W
Initial Value
0
N/A
0000
0
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