參數(shù)資料
型號: MR80C32E-16P883
廠商: TEMIC SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 16 MHz, MICROCONTROLLER, CQCC44
文件頁數(shù): 68/176頁
文件大?。?/td> 2962K
代理商: MR80C32E-16P883
16
2535J–AVR–08/10
ATtiny13
The 32 general purpose working registers, 64 I/O Registers, and the 64 bytes of internal data
SRAM in the ATtiny13 are all accessible through all these addressing modes. The Register File
Figure 5-2.
Data Memory Map
5.2.1
Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clkCPU cycles as described in Figure 5-3.
Figure 5-3.
On-chip Data SRAM Access Cycles
5.3
EEPROM Data Memory
The ATtiny13 contains 64 bytes of data EEPROM memory. It is organized as a separate data
space, in which single bytes can be read and written. The EEPROM has an endurance of at
least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described
in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and
the EEPROM Control Register. For a detailed description of Serial data downloading to the
EEPROM, see page 105.
5.3.1
EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space.
32 Registers
64 I/O Registers
Internal SRAM
(64 x 8)
0x0000 - 0x001F
0x0020 - 0x005F
0x009F
0x0060
Data Memory
clk
WR
RD
Data
Address
Address valid
T1
T2
T3
Compute Address
Read
Wr
ite
CPU
Memory Access Instruction
Next Instruction
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