參數(shù)資料
型號： MR80C52XXX-36P883R
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQCC44
封裝： LCC-44
文件頁數(shù)： 19/132頁
文件大?。?/td> 10886K
代理商： MR80C52XXX-36P883R
189
ATmega8535(L)
2502K–AVR–10/06
Master Transmitter Mode
In the Master Transmitter mode, a number of data bytes are transmitted to a Slave
Receiver (see Figure 86). In order to enter a Master mode, a START condition must be
transmitted. The format of the following address packet determines whether Master
Transmitter or Master Receiver mode is to be entered. If SLA+W is transmitted, MT
mode is entered, if SLA+R is transmitted, MR mode is entered. All the status codes
mentioned in this section assume that the prescaler bits are zero or are masked to zero.
Figure 86. Data Transfer in Master Transmitter Mode
A START condition is sent by writing the following value to TWCR:
TWEN must be set to enable the Two-wire Serial Interface, TWSTA must be written to
one to transmit a START condition and TWINT must be written to one to clear the
TWINT Flag. The TWI will then test the Two-wire Serial Bus and generate a START
condition as soon as the bus becomes free. After a START condition has been transmit-
ted, the TWINT Flag is set by hardware, and the status code in TWSR will be 0x08 (see
Table 75). In order to enter MT mode, SLA+W must be transmitted. This is done by writ-
ing SLA+W to TWDR. Thereafter the TWINT bit should be cleared (by writing it to one)
to continue the transfer. This is accomplished by writing the following value to TWCR:
When SLA+W have been transmitted and an acknowledgement bit has been received,
TWINT is set again and a number of status codes in TWSR are possible. Possible sta-
tus codes in Master mode are 0x18, 0x20, or 0x38. The appropriate action to be taken
for each of these status codes is detailed in Table 75.
When SLA+W has been successfully transmitted, a data packet should be transmitted.
This is done by writing the data byte to TWDR. TWDR must only be written when
TWINT is high. If not, the access will be discarded, and the Write Collision bit (TWWC)
will be set in the TWCR Register. After updating TWDR, the TWINT bit should be
cleared (by writing it to one) to continue the transfer. This is accomplished by writing the
following value to TWCR:
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
Value
1
X1
0
X1
0
X
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
Value
1
X0
0
X1
0
X
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
Value
1
X0
0
X1
0
X
Device 1
MASTER
TRANSMITTER
Device 2
SLAVE
RECEIVER
Device 3
Device n
SDA
SCL
........
R1
R2
V
CC
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