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參數(shù)資料
| 型號(hào)： | MR80C52XXX-36P883R |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQCC44 |
| 封裝： | LCC-44 |
| 文件頁(yè)數(shù)： | 54/132頁(yè) |
| 文件大?。?/td> | 10886K |
| 代理商： | MR80C52XXX-36P883R |
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22
7593L–AVR–09/12
AT90USB64/128
An optional external data SRAM can be used with the Atmel AT90USB64/128. This SRAM will
occupy an area in the remaining address locations in the 64K address space. This area starts at
the address following the internal SRAM. The Register file, I/O, Extended I/O and Internal SRAM
occupies the lowest 4,352/8,448 bytes, so when using 64KB (65,536 bytes) of External Memory,
61,184/57,088 Bytes of External Memory are available. See “External memory interface” on
page 31 for details on how to take advantage of the external memory map.
When the addresses accessing the SRAM memory space exceeds the internal data memory
locations, the external data SRAM is accessed using the same instructions as for the internal
data memory access. When the internal data memories are accessed, the read and write strobe
pins (PE0 and PE1) are inactive during the whole access cycle. External SRAM operation is
enabled by setting the SRE bit in the XMCRA Register.
Accessing external SRAM takes one additional clock cycle per byte compared to access of the
internal SRAM. This means that the commands LD, ST, LDS, STS, LDD, STD, PUSH, and POP
take one additional clock cycle. If the Stack is placed in external SRAM, interrupts, subroutine
calls and returns take three clock cycles extra because the three-byte program counter is
pushed and popped, and external memory access does not take advantage of the internal pipe-
line memory access. When external SRAM interface is used with wait-state, one-byte external
access takes two, three, or four additional clock cycles for one, two, and three wait-states
respectively. Interrupts, subroutine calls and returns will need five, seven, or nine clock cycles
more than specified in the Instruction set Manual for one, two, and three wait-states.
The five different addressing modes for the data memory cover: Direct, Indirect with Displace-
ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register file,
registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address given
by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O registers, and the 8,192 bytes of internal data
SRAM in the AT90USB64/128 are all accessible through all these addressing modes. The Reg-
ister File is described in “General purpose register file” on page 14.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MQ80C52XXX-36SHXXX | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44 |
| MC80C32E-16SHXXX:D | 8-BIT, 16 MHz, MICROCONTROLLER, CDIP40 |
| MR80C52XXX-36SCD | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQCC44 |
| MD80C32-16SHXXX | 8-BIT, 16 MHz, MICROCONTROLLER, CDIP40 |
| MR80C32E-20/883:RD | 8-BIT, 20 MHz, MICROCONTROLLER, CQCC44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MR80C86 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MR80C86/B | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述:Microprocessor, 16 Bit, 44 Pin, Ceramic, LCC |
| MR80C86-2 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MR80C86-2/883 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MR80C86-2/B | 制造商:Intersil Corporation 功能描述:MPU 80C86 16BIT CMOS 8MHZ 44PLCC - Rail/Tube |
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