參數(shù)資料
型號(hào)： MSC8126VT8000
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 0-BIT, 500 MHz, OTHER DSP, PBGA431
封裝： 20 X 20 MM, LEAD FREE, PLASTIC, FCBGA-431
文件頁(yè)數(shù)： 11/48頁(yè)
文件大小： 1138K
代理商： MSC8126VT8000
Electrical Characteristics
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 15
Freescale Semiconductor
19
2.5.4
Reset Timing
The MSC8126 has several inputs to the reset logic:
Power-on reset (PORESET)
External hard reset (HRESET)
External soft reset (SRESET)
Software watchdog reset
Bus monitor reset
Host reset command through JTAG
All MSC8126 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset.
The reset status register indicates the most recent sources to cause a reset. Table 10 describes the reset sources.
Table 11 summarizes the reset actions that occur as a result of the different reset sources.
Table 9. System Clock Parameters
Characteristic
Min
Max
Unit
Phase jitter between BCLK and CLKIN
—
0.3
ns
CLKIN frequency
20
MHz
CLKIN slope
—3
ns
PLL input clock (after predivider)
20
100
MHz
PLL output frequency (VCO output)
400 MHz core
500 MHz core
800
1600
2000
MHz
CLKOUT frequency jitter1
—
200
ps
CLKOUT phase jitter1 with CLKIN phase jitter of ±100 ps
—
500
ps
Notes:
1.
Peak-to-peak.
2.
Not tested. Guaranteed by design.
Table 10. Reset Sources
Name
Direction
Description
Power-on reset
(PORESET)
Input
Initiates the power-on reset flow that resets the MSC8126 and configures various attributes of the
MSC8126. On PORESET, the entire MSC8126 device is reset. SPLL states is reset, HRESET and
SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The
clock mode (MODCK bits), reset configuration mode, boot mode, Chip ID, and use of either a DSI 64
bits port or a System Bus 64 bits port are configured only when PORESET is asserted.
External hard
reset (HRESET)
Input/ Output
Initiates the hard reset flow that configures various attributes of the MSC8126. While HRESET is
asserted, SRESET is also asserted. HRESET is an open-drain pin. Upon hard reset, HRESET and
SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The
most configurable features are reconfigured. These features are defined in the 32-bit hard reset
configuration word described in Hard Reset Configuration Word section of the Reset chapter in the
MSC8126 Reference Manual.
External soft reset
(SRESET)
Input/ Output
Initiates the soft reset flow. The MSC8126 detects an external assertion of SRESET only if it occurs
while the MSC8126 is not asserting reset. SRESET is an open-drain pin. Upon soft reset, SRESET is
driven, the SC140 extended cores are reset, and system configuration is maintained.
Software
watchdog reset
Internal
When the MSC8126 watchdog count reaches zero, a software watchdog reset is signalled. The
enabled software watchdog event then generates an internal hard reset sequence.
Bus monitor reset
Internal
When the MSC8126 bus monitor count reaches zero, a bus monitor hard reset is asserted. The
enabled bus monitor event then generates an internal hard reset sequence.
Host reset
command through
the TAP
Internal
When a host reset command is written through the Test Access Port (TAP), the TAP logic asserts the
soft reset signal and an internal soft reset sequence is generated.
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