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參數(shù)資料
| 型號： | MSC8126VT8000 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 0-BIT, 500 MHz, OTHER DSP, PBGA431 |
| 封裝： | 20 X 20 MM, LEAD FREE, PLASTIC, FCBGA-431 |
| 文件頁數(shù)： | 13/48頁 |
| 文件大?。?/td> | 1138K |
| 代理商： | MSC8126VT8000 |
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MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 15
Electrical Characteristics
Freescale Semiconductor
20
2.5.4.1
Power-On Reset (PORESET) Pin
Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 16 CLKIN cycles after
VDD and VDDH are both at their nominal levels.
2.5.4.2
Reset Configuration
The MSC8126 has two mechanisms for writing the reset configuration:
Through the direct slave interface (DSI)
Through the system bus. When the reset configuration is written through the system bus, the MSC8126 acts as a
configuration master or a configuration slave. If configuration slave is selected, but no special configuration word is
written, a default configuration word is applied.
Fourteen signal levels (see Chapter 1 for signal description details) are sampled on PORESET deassertion to define the Reset
Configuration Mode and boot and operating conditions:
RSTCONF
CNFGS
DSISYNC
DSI64
CHIP_ID[0–3]
BM[0–2]
SWTE
MODCK[1–2]
Table 11. Reset Actions for Each Reset Source
Reset Action/Reset Source
Power-On
Reset
(PORESET)
Hard Reset (HRESET)
Soft Reset (SRESET)
External only
External or Internal
(Software Watchdog or
Bus Monitor)
External
JTAG Command:
EXTEST, CLAMP, or
HIGHZ
Configuration pins sampled (Refer to
Section 2.5.4.1 for details).
Yes
NoNoNo
SPLL state reset
Yes
No
System reset configuration write through
the DSI
Yes
NoNoNo
System reset configuration write though
the system bus
Yes
No
HRESET driven
Yes
No
SIU registers reset
Yes
No
IPBus modules reset (TDM, UART,
Timers, DSI, IPBus master, GIC, HS, and
GPIO)
Yes
SRESET driven
Yes
Depends on command
SC140 extended cores reset
Yes
MQBS reset
Yes
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