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參數(shù)資料
| 型號(hào)： | MSC8126VT8000 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 0-BIT, 500 MHz, OTHER DSP, PBGA431 |
| 封裝： | 20 X 20 MM, LEAD FREE, PLASTIC, FCBGA-431 |
| 文件頁數(shù)： | 38/48頁 |
| 文件大?。?/td> | 1138K |
| 代理商： | MSC8126VT8000 |
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Hardware Design Considerations
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 15
Freescale Semiconductor
43
–
The maximum load on CLKOUT must not exceed 10 pF.
–
Use a zero-delay buffer with a jitter less than 0.3 ns.
— All clock modes are valid in this clock scheme.
Note:
See the Clock chapter in the MSC8122 Reference Manual for details.
If the 60x-compatible system bus is not used and SIUMCR[PBSE] is set, PPBS can be disconnected. Otherwise, it
should be pulled up.
The following signals: SWTE, DSISYNC, DSI64, MODCK[1–2], CNFGS, CHIPID[0–3], RSTCONF and BM[0–2] are
used to configure the MSC8126 and are sampled on the deassertion of the PORESET signal. Therefore, they should
be tied to GND or VDDH or through a pull-down or a pull-up resistor until the deassertion of the PORESET signal.
When they are used, INT_OUT (if SIUMCR[INTODC] is cleared), NMI_OUT, and IRQxx (if not full drive) signals must
be pulled up.
When the Ethernet controller is enabled and the SMII mode is selected, GPIO10 and GPIO14 must not be connected
externally to any signal line.
Note:
For details on configuration, see the MSC8126 User’s Guide and MSC8126 Reference Manual. For additional
information, refer to the MSC8126 Design Checklist (AN2903).
3.4
External SDRAM Selection
The external bus speed implemented in a system determines the speed of the SDRAM used on that bus. However, because of
differences in timing characteristics among various SDRAM manufacturers, you may have use a faster speed rated SDRAM to
assure efficient data transfer across the bus. For example, for 166 MHz operation, you may have to use 183 or 200 MHz
SDRAM. Always perform a detailed timing analysis using the MSC8126 bus timing values and the manufacturer specifications
for the SDRAM to ensure correct operation within your system design. The output delay listed in SDRAM specifications is
usually given for a load of 30 pF. Scale the number to your specific board load using the typical scaling number provided by
the SDRAM manufacturer.
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