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MSM66573 Family User's Manual
Chapter 12 Serial Port Functions
12.6 SIO0, SIO1 Operation
12.6.1 Transmit Operation
UART mode
Figure 12-10 shows the timing diagram of operation during UART transmission.
The clock pulse from the baud rate generator (timer 3 or timer 4) or from an external input
is divided by 16 to generate the transmit shift clock.
If an external clock is to be used with the UART mode, input the clock to the external clock
input pin (RXC0) for SIO0, or the receive clock I/O pin (RXC1) for SIO1. The externally input
clock is processed as shown in figure 12-11, and is input to the 1/16 dividing counter (or 1/
n dividing counter in the case of SIO1) as the baud rate clock.
In synchronization with the transmit shift clock that has been generated, the transmission
circuit controls transmission of the transmit data.
The SnBUF write signal (a signal that is output when an instruction to write to SnBUF is
executed, for example "STB A, SnBUF") acts as a trigger to start transmission.
One CPU clock after the write signal is generated, transmit data in SnBUF is set in the
transmit shift register. At this time, synchronized to the signal indicating the beginning of
an instruction (M1S1), a transmit buffer empty signal is generated.
After the transmit data is set (after the fall of the data transfer signal to the transmit shift
register), synchronized to the falling edge of the next transmit shift clock, the start bit is
output from the transmit data output pin (TXDn). Thereafter, as specified by STnCON, the
transmit data (LSB first), parity bit, and finally the stop bit are output to complete the
transmission of one frame.
At this time, if the next transmit data has not been written to SnBUF, a transmit complete
signal is generated in synchronization with M1S1, and the transmission is completed.
Because generation of the transmit shift clock is always unrelated to writes to SnBUF, from
the time when transmit data is written to SnBUF until the start bit is output, there is a delay
of a maximum of 16 baud rate clocks.
Because each of SIO0 and SIO1 has SnBUF and the transmit shift register which are
designed in a duplex construction, during a transmission it is possible to write the next
transmit data to SnBUF. If SnBUF is written to during a transmission, after the current one
frame transmission is completed, the next transmit data will be automatically set in the
transmitted shift register, and the data transmission will continue. After one frame of data
is transmit, if the next data to be transmitted has been written to SnBUF, the transmit
complete signal will not be generated.
Figure 12-14 shows the timing diagram of operation during continuous transmission.