17-1
MSM66573 Family User's Manual
Chapter 17 Bus Port Functions
17
17 Bus Port Functions
17.1 Overview
The MSM66573 family can externally expand program memory (usually ROM) up to a
maximum of 1MB and data memory (usually RAM) up to a maximum of 1MB.
Bus ports (A0 to A19, D0 to D7) and control signals (
PSEN, RD, WR) are used to access
the external program memory and external data memory.
Bus ports are assigned as the secondary functions of port 0 (P0), port 1 (P1), port 2 (P2)
and port 4 (P4). The 20 address (A0 to A19) lines and 8 data (D0 to D7) lines of the bus
are separate. Unnecessary upper addresses can be reset as normal I/O ports.
PSEN (P3_1) is used as a strobe signal to read the external program memory. RD (P3_2)
and
WR (P3_3) are used as read and write strobes for external data memory.
17.2 Port Operation
17.2.1 Port Operation When Accessing Program Memory
When accessing internal program memory (addresses 0H to 0FFFFH* with the
EA pin at
a high level), P0, P1, P2, P3_1 and P4 operate as I/O ports.
When accessing external program memory (the
EA pin at a low level or addresses 10000H
to 0FFFFFH* with the
EA pin at a high level), P0 operates as the program data input port,
P1, P2, and P4 operate as address output ports, and P3_1 operates as the
PSEN output
port.
If the
EA pin is at a low level, P0, P1, P2, P3_1 and P4 are automatically switched (secondary
function control registers and mode registers are set) to bus port and control signal
functions (hereafter referred to as bus port functions) when reset (
RES signal input,
execution of a BRK instruction, overflow of the watchdog timer, opcode trap). If the
EA pin
is at a high level, before external program memory is accessed, it is necessary to switch
to bus port functions by setting secondary function control registers and mode registers.
Of the ports that are automatically set as bus port functions when the
EA pin is at a low level,
if upper address or other output is unnecessary, then after reset, those ports can be
operated as I/O ports by resetting their secondary function control register.
Table 17-1 lists the operation of P0, P1, P2, P3_1 and P4 during a program memory access.