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MSM66573 Family User's Manual
Chapter 3 CPU Control Functions
3
After STOP mode is released, if the master interrupt enable flag (MIE in PSW) has been
set to "1", processing of the requested maskable interrupt is performed.
If the master interrupt enable flag (MIE in PSW) has been reset to "0", the next instruction
(following the instruction that set the STOP mode (that set bit 0 (STP) of SBYCON to "1"))
is executed. However, if the STOP mode has been set during the processing of a non-
maskable interrupt routine, the STOP mode can be released by an interrupt request. After
being released, the next instruction in the non-maskable interrupt routine (following the
instruction that changed the mode to the STOP mode) will be executed. If interrupt priority
is set (bit 7 (MIPF) of EXI2CON set to "1") and the STOP mode is set during a high priority
interrupt routine, a low priority interrupt request can release the STOP mode. However,
after release the low priority interrupt is suspended and the next instruction in the high
priority interrupt routine will be executed.
If an interrupt request from the high-speed STOP mode (main clock oscillation terminated)
causes the STOP mode to be released, operation will continue after waiting for the
oscillation stabilization time of the main clock (OSCCLK) as set by SBYCON. The STOP
mode can also be entered while the main clock continues to oscillate (quick activating
STOP mode). In this case, when returning from the STOP mode, activation is possible
without waiting for the oscillation stabilization time of the main clock.
Figure 3-4 shows the STOP mode timing diagram.
If the STOP mode is released by reset due to the
RES pin input, the CPU will perform the
reset processing. If the
RES pin input is to be used to release the STOP mode with main
clock oscillation halted, apply a low level to the
RES pin until the main clock oscillation
stabilizes. In the case of a Flash ROM product, apply a low level to the
RES pin for 50 ms.
Instruction
execution
Dummy cycle
Oscillation
halted
Dummy cycle
Instruction
execution
Main clock
(OSCCLK)
M1S1
(Signal that indicates
beginning of instruction)
SBYCON.STP
Interrupt request
(NMI, IRQ and IE)
Operating state
Port output mode
Timer operation
Timer halted
Timer operation
Port floating
(when FLT = "1")
Port output mode
*Oscillation
stabilization time
STOP mode
* Oscillation stabilization time is the time until the main clock starts oscillating, plus the time of
the number of clocks set by OST0 and OST1.
Figure 3-4 STOP Mode Timing Diagram
(When released by an interrupt)