參數資料
型號: MSM82C59A-2GS-K
廠商: OKI ELECTRIC INDUSTRY CO LTD
元件分類: 中斷控制器
英文描述: 80C85AH; 80C86A; 80C88A COMPATIBLE, INTERRUPT CONTROLLER, PDSO32
封裝: PLASTIC, SSOP-32
文件頁數: 13/29頁
文件大?。?/td> 252K
代理商: MSM82C59A-2GS-K
20/29
Semiconductor
MSM82C59A-2RS/GS/JS
FEDL82C59A-2-03
IS7 IS6 IS5 IS4 IS3 IS2 IS1 IS0
0
1
0
1
0
7
6
5
4
3
2
1
0
Lowest
Highest
IS Status
Priority Status
Before Rotation
(IR4 the highest priority requesting service)
IS7 IS6 IS5 IS4 IS3 IS2 IS1 IS0
0
1
0
2
1
0
7
6
5
4
3
Lowest
Highest
IS Status
Priority Status
After Rotation
(IR4 was serviced, all other priorities rotated correspondingly)
(11) Specific Rotation (Specific Priority)
All priority levels can be changed by programming the lowest priority level (Set Priority
Command in OCW2). For example, if IR5 is programmed as the device of lowest priority,
IR6 will have the highest priority. In this mode, the internal status can be updated during
OCW2 by software control. This is unrelated, however, to the EOI command in the same
OCW2.
Priority level can also be changed by using the OCW2 Rotate On Specific EOI command.
(12) Interrupt Mask
Interrupt inputs can be masked individually by Interrupt Mask Registers (IMR)
programmed through the OCW1. Each interrupt channel is masked (disabled) when the
respective IMR bit is set to “1”. IR0 is masked by bit 0, and IR1 is masked by bit 1. Masking
of any particular channel has no effect on other channels.
相關PDF資料
PDF描述
MSM82C84A-2GS-K 8 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO24
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參數描述
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