參數資料
型號: MSM82C59A-2GS-K
廠商: OKI ELECTRIC INDUSTRY CO LTD
元件分類: 中斷控制器
英文描述: 80C85AH; 80C86A; 80C88A COMPATIBLE, INTERRUPT CONTROLLER, PDSO32
封裝: PLASTIC, SSOP-32
文件頁數: 4/29頁
文件大小: 252K
代理商: MSM82C59A-2GS-K
12/29
Semiconductor
MSM82C59A-2RS/GS/JS
FEDL82C59A-2-03
Contents of the Second Interrupt vector byte
The higher address of the interrupt service routine programmed by the second bytes (A8 -
A15) of the initialization sequence is released to the data bus.
D7
D6
D5
D4
D3
D2
D1
D0
A15
A14
A13
A12
A11
A10
A9
A8
Contents of the Third Interrupt Vector Byte
86 Mode (MSM80C86A-10/88A-10)
Apart from the two interrupt acknowledge cycles and the absence of a CALL operation
code, the 86 mode is the same as the 85 mode. The first INTA cycle freezes interrupt status
to resolve the priority internally in the same way as in 85 mode. When the device is used
as a master, an interrupt code is issued to the cascade line at the end of the INTA pulse.
During this first cycle, the data bus buffer is kept at high impedance without any data to
the CPU. During the second INTA cycle, the MSM82C59A-2 sends a byte of interrupt code
to the CPU. Note that in 86 mode, the Address Interval (ADI) control status is ignored and
A5-A10 is not used.
IR
Interval = 4
D7
D6
D5
D4
D3
D2
D1
D0
7A7
A6
A5
111
0
A7
A6
A5
110
0
A7
A6
A5
101
0
A7
A6
A5
100
0
A7
A6
A5
011
0
A7
A6
A5
010
0
A7
A6
A5
001
0
6
5
4
3
2
1
A7
A6
A5
000
0
IR
Interval = 8
D7
D6
D5
D4
D3
D2
D1
D0
7A7
A6
1
110
0
A7
A6
1
100
0
A7
A6
1
010
0
A7
A6
1
000
0
A7
A6
0
110
0
A7
A6
0
100
0
A7
A6
0
010
0
6
5
4
3
2
1
A7
A6
0
000
0
相關PDF資料
PDF描述
MSM82C84A-2GS-K 8 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO24
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