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參數(shù)資料
| 型號： | MSM82C59A-2GS-K |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 中斷控制器 |
| 英文描述： | 80C85AH; 80C86A; 80C88A COMPATIBLE, INTERRUPT CONTROLLER, PDSO32 |
| 封裝： | PLASTIC, SSOP-32 |
| 文件頁數(shù)： | 14/29頁 |
| 文件大?。?/td> | 252K |
| 代理商： | MSM82C59A-2GS-K |
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Semiconductor
MSM82C59A-2RS/GS/JS
FEDL82C59A-2-03
(13) Special Mask Mode
In some applications, there is a need for dynamic updating of the system’s priority level
structure by software control during execution of an interrupt service routine. For
example, it may be necessary to inhibit the lower priority requests for part of the execution
of a certain routine while enabling for another part. In this case, it is difficult to enable all
lower priority requests if the IS bit has not yet been reset by the EOI command after an
interrupt request has been acknowledge (during execution of a service routine). All of
these requests would normally be disabled.
Hence the use of the Special Mask mode. When a mask bit is set by OCW1 in this mode,
the corresponding interrupt level requests are disabled. And all other unmasked level
requests (at both higher and lower priority levels) are enabled. Interrupts can thus be
enabled selectively by loading the mask register.
In this mode, the specific EOI Command should be used.
This Special Mask mode is set by OCW3 ESMM = 1 and SMM = 1, and reset by ESMM =
1 and SMM = 0.
(14) POLL Command
In this mode, the INT output is not used, the internal interrupt enable F/F of the
microprocessor is reset, and interrupt inputs are disabled. Servicing the I/O device is
executed by software using the Poll command.
The Poll command is issued by setting P in OCW3 to “1”. The MSM82C59A-2 regards the
next RD pulse as reception of an interrupt, and if there is a request, the corresponding IS
bit is set and the priority level is read out. Interrupts are frozen between WR and RD.
This mode is useful when there is a command routine for a number of levels, and the INTA
sequence is not required. ROM space can thus be saved.
D7
D6
D5
D4
D3
D2
D1
D0
1
0
W2 W1 W0
Poll Word
W0 thru W2:
1:
Binary coded highest priority level of service
being requested.
Set to "1" when there is an interrupt.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSM82C84A-2GS-K | 8 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO24 |
| MSM82C84A-2JS | OTHER CLOCK GENERATOR, PQCC20 |
| MSM83C154-XXJS | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44 |
| MSM83C154-1-XXJS | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44 |
| MSM83C154S-XXXJS | 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PQCC44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM82C59A-2JS | 制造商:ROHM Semiconductor 功能描述: |
| MSM82C59A-2JSDR1 | 制造商:ROHM Semiconductor 功能描述: |
| MSM82C59A-2JS-DR1 | 制造商:ROHM Semiconductor 功能描述:PROGRAMMABLE INTERRUPT CONTROLLER |
| MSM82C59A-2RS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:PROGRAMMABLE INTERRUPT CONTROLLER |
| MSM82C59A-2RS-7 | 制造商:ROHM Semiconductor 功能描述:PROGRAMMABLE INTERRUPT CONTROLLER |
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