參數(shù)資料
型號(hào)： MSM82C59A-2GS-K
廠(chǎng)商： OKI ELECTRIC INDUSTRY CO LTD
元件分類(lèi)： 中斷控制器
英文描述： 80C85AH; 80C86A; 80C88A COMPATIBLE, INTERRUPT CONTROLLER, PDSO32
封裝： PLASTIC, SSOP-32
文件頁(yè)數(shù)： 2/29頁(yè)
文件大?。?/td> 252K
代理商： MSM82C59A-2GS-K
10/29
Semiconductor
MSM82C59A-2RS/GS/JS
FEDL82C59A-2-03
OPERATION DESCRIPTION
The MSM82C59A-2 has been designed for real time interrupt driven microcomputer systems.
The MSM82C59A-2 is capable of handling up to 8 levels of interrupt requests, and can be
expanded to cover a maximum of 64 levels when connected to other MSM82C59A-2 devices.
Programming involves the use of system software in the same way as other microcomputer
peripheral I/O devices. Selection of priority mode involves program execution, and enables the
method of requesting interrupts to be processed by the MSM82C59A-2 to be suitably configured
for system requirements. That is, the priority mode can be dynamically updated or reconfigured
during the main program at any time. A complete interrupt structure can be defined as
required, based on the entire system environment.
(1) Functional Description of Each Block
(2) Interrupt Sequence
The major features of the MSM82C59A-2 used in microcomputer systems are the
programmability and the addressing capability of interrupt routines. This latter feature
enables direct or indirect jumping to specific interrupt routines without polling the
interrupt devices. The operational sequence during an interrupt varies for different CPUs.
The procedure for the 85 system (MSM80C85AH) is outlined below.
(i)
One or more interrupt requests (IR0 thru IR7) becomes high, and the corresponding IRR
bit is set.
(ii) The MSM82C59A-2 evaluates these requests, and sends an INT signal to the CPU if the
request is judged to be suitable.
(iii) The CPU issues an INTA output pulse upon reception of the INT signal.
(iv) Upon reception of the INTA signal from the CPU, the MSM82C59A-2 releases the
CALL instruction code (11001101) to the 8-bit data bus.
Block Name
Description of Function
IRR, ISR
IR input line interrupts are processed by a cascaded interrupt request register
(IRR) and the in-service register (ISR). The IRR stores all request levels where
interrupt service is requested, and the ISR stores all interrupt levels being
serviced.
Priority Resolver
This logic block determines the priority level of the bits set in the IRR. The
highest priority level is selected, and the corresponding ISR bit is set during
INTA pulses.
Read/Write Logic
This block is capable of receiving commands from the CPU. These command
words (ICW) and the operation command words (OCW) store the various
control formats for MSM82C59A-2 operations. This block is also used to
transfer the status of the MSM82C59A-2 to the Data Bus.
Cascade Buffer Comparator
This functional block is involved in the output and comparison of all
MSM82C59A-2 IDs used in the system. These three I/O pins (CAS0 thru CAS2)
are outputs when the MSM82C59A-2 operates as a master, and inputs when it
operates as a slave. When operating as a master, the MSM82C59A-2 sends a
slave ID output to the slave where an interrupt has been applied.
Furthermore, the selected slave sends the preprogrammed subroutine address
onto the data bus during next one or two INTA pulses from the CPU.
相關(guān)PDF資料
PDF描述
MSM82C84A-2GS-K 8 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO24
MSM82C84A-2JS OTHER CLOCK GENERATOR, PQCC20
MSM83C154-XXJS 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44
MSM83C154-1-XXJS 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44
MSM83C154S-XXXJS 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PQCC44
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MSM82C59A-2JS 制造商:ROHM Semiconductor 功能描述:
MSM82C59A-2JSDR1 制造商:ROHM Semiconductor 功能描述:
MSM82C59A-2JS-DR1 制造商:ROHM Semiconductor 功能描述:PROGRAMMABLE INTERRUPT CONTROLLER
MSM82C59A-2RS 制造商:OKI 制造商全稱(chēng):OKI electronic componets 功能描述:PROGRAMMABLE INTERRUPT CONTROLLER
MSM82C59A-2RS-7 制造商:ROHM Semiconductor 功能描述:PROGRAMMABLE INTERRUPT CONTROLLER
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