參數(shù)資料
型號(hào)： MSP430A018IPN
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 8 MHz, RISC MICROCONTROLLER, PQFP80
封裝： GREEN, PLASTIC, QFP-80
文件頁(yè)數(shù)： 29/73頁(yè)
文件大?。?/td> 1284K
代理商： MSP430A018IPN
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B APRIL 2004 REVISED JUNE 2007
35
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, built-in reference
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
V
Positive built-in reference
REF2_5V = 1 for 2.5 V
IVREF+max ≤ IVREF+≤ IVREF+min
VCC = 3 V
2.4
2.5
2.6
V
VREF+
Positive built in reference
voltage output
REF2_5V = 0 for 1.5 V
IVREF+max ≤ IVREF+≤ IVREF+min
VCC = 2.2 V/3 V
1.44
1.5
1.56
V
AVCC minimum voltage,
REF2_5V = 0, IVREF+max ≤ IVREF+≤ IVREF+min
2.2
AVCC(min)
AVCC minimum voltage,
Positive built-in reference
REF2_5V = 1, IVREF+min ≥ IVREF+≥ 0.5mA
2.8
V
AVCC(min)
Positive built in reference
active
REF2_5V = 1, IVREF+min ≥ IVREF+≥ 1mA
2.9
V
I
Load current out of VREF+
VCC = 2.2 V
0.01
0.5
mA
IVREF+
Load current out of VREF+
terminal
VCC = 3 V
0.01
1
mA
IVREF+ = 500 μA +/ 100 μA
Analog input voltage 0 75 V;
VCC = 2.2 V
±2
LSB
I
Load-current regulation
Analog input voltage ~0.75 V;
REF2_5V = 0
VCC = 3 V
±2
LSB
IL(VREF)+
Load current regulation
VREF+ terminal
IVREF+ = 500 μA ± 100 μA
Analog input voltage ~1.25 V;
REF2_5V = 1
VCC = 3 V
±2
LSB
I
Load current regulation
IVREF+ =100 μA → 900 μA,
C
5
μF ax 05xV
V
3V
20
ns
IDL(VREF) +
Load current regulation
VREF+ terminal
CVREF+=5 μF, ax ~0.5 x VREF+
Error of conversion result
≤ 1 LSB
VCC = 3 V
20
ns
CVREF+
Capacitance at pin VREF+
(see Note 1)
REFON =1,
0 mA
≤ IVREF+ ≤ IVREF+max
VCC = 2.2 V/3 V
5
10
μF
TREF+
Temperature coefficient of
built-in reference
IVREF+ is a constant in the range of
0 mA
≤ IVREF+ ≤ 1 mA
VCC = 2.2 V/3 V
±100 ppm/°C
tREFON
Settle time of internal
reference voltage (see
Figure 18 and Note 2)
IVREF+ = 0.5 mA, CVREF+ = 10 μF,
VREF+ = 1.5 V, VAVCC = 2.2 V
17
ms
NOTES:
1. The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses
two capacitors between pins VREF+ and AVSS and VREF/VeREF and AVSS: 10 μF tantalum and 100 nF ceramic.
2. The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load.
CVREF+
1
μF
0
1 ms
10 ms
100 ms
tREFON
tREFON ≈ .66 x CVREF+ [ms] with CVREF+ in μF
100
μF
10
μF
Figure 18. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+
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