參數(shù)資料
型號： MSP430A018IPN
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 8 MHz, RISC MICROCONTROLLER, PQFP80
封裝： GREEN, PLASTIC, QFP-80
文件頁數(shù)： 45/73頁
文件大?。?/td> 1284K
代理商： MSP430A018IPN
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B APRIL 2004 REVISED JUNE 2007
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
MSP430FG43x Terminal Functions (Continued)
TERMINAL
PN
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
P3.3/UCLK0/S28
40
I/O
General-purpose digital I/O / ext. clock i/p—USART0/UART or SPI mode, clock o/p—USART0/SPI mode
/ LCD segment output 28
P3.2/SOMI0/S29
41
I/O
General-purpose digital I/O / slave out/master in of USART0/SPI mode / LCD segment output 29
P3.1/SIMO0/S30
42
I/O
General-purpose digital I/O / slave out/master out of USART0/SPI mode / LCD segment output 30
P3.0/STE0/S31
43
I/O
General-purpose digital I/O / slave transmit enable-USART0/SPI mode / LCD segment output 31
COM0
44
O
Common output, COM03 are used for LCD backplanes.
P5.2/COM1
45
I/O
General-purpose digital I/O / common output, COM03 are used for LCD backplanes.
P5.3/COM2
46
I/O
General-purpose digital I/O / common output, COM03 are used for LCD backplanes.
P5.4/COM3
47
I/O
General-purpose digital I/O / common output, COM03 are used for LCD backplanes.
R03
48
I
Input port of fourth positive (lowest) analog LCD level (V5)
P5.5/R13
49
I/O
General-purpose digital I/O / input port of third most positive analog LCD level (V4 or V3)
P5.6/R23
50
I/O
General-purpose digital I/O / input port of second most positive analog LCD level (V2)
P5.7/R33
51
I/O
General-purpose digital I/O / output port of most positive analog LCD level (V1)
DVCC2
52
Digital supply voltage, positive terminal.
DVSS2
53
Digital supply voltage, negative terminal.
P2.5/URXD0
54
I/O
General-purpose digital I/O / receive data in—USART0/UART mode
P2.4/UTXD0
55
I/O
General-purpose digital I/O / transmit data out—USART0/UART mode
P2.3/TB2
56
I/O
General-purpose digital I/O / Timer_B3 CCR2.
Capture: CCI2A/CCI2B input, compare: Out2 output
P2.2/TB1
57
I/O
General-purpose digital I/O / Timer_B3 CCR1.
Capture: CCI1A/CCI1B input, compare: Out1 output
P2.1/TB0
58
I/O
General-purpose digital I/O / Timer_B3 CCR0.
Capture: CCI0A/CCI0B input, compare: Out0 output
P2.0/TA2
59
I/O
General-purpose digital I/O / Timer_A
Capture: CCI2A input, compare: Out2 output
P1.7/CA13
60
I/O
General-purpose digital I/O / Comparator_A input
P1.6/CA0
61
I/O
General-purpose digital I/O / Comparator_A input
P1.5/TACLK/
ACLK
62
I/O
General-purpose digital I/O / Timer_A, clock signal TACLK input /
ACLK output (divided by 1, 2, 4, or 8)
P1.4/TBCLK/
SMCLK
63
I/O
General-purpose digital I/O / input clock TBCLK—Timer_B3 / submain system clock SMCLK output
P1.3/TBOUTH/
SVSOUT
64
I/O
General-purpose digital I/O / switch all PWM digital output ports to high impedance—Timer_B3 TB0 to TB2
/ SVS: output of SVS comparator
P1.2/TA1
65
I/O
General-purpose digital I/O / Timer_A, Capture: CCI1A, compare: Out1 output
P1.1/TA0/MCLK
66
I/O
General-purpose digital I/O / Timer_A. Capture: CCI0B / MCLK output. Note: TA0 is only an input on this
pin / BSL receive
P1.0/TA0
67
I/O
General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output / BSL transmit
XT2OUT
68
O
Output terminal of crystal oscillator XT2
XT2IN
69
I
Input port for crystal oscillator XT2. Only standard crystals can be connected.
TDO/TDI
70
I/O
Test data output port. TDO/TDI data output or programming data input terminal
TDI/TCLK
71
I
Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TMS
72
I
Test mode select. TMS is used as an input port for device programming and test.
TCK
73
I
Test clock. TCK is the clock input port for device programming and test.
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