參數(shù)資料
型號: MSP430A018IPN
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 8 MHz, RISC MICROCONTROLLER, PQFP80
封裝: GREEN, PLASTIC, QFP-80
文件頁數(shù): 73/73頁
文件大小: 1284K
代理商: MSP430A018IPN
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B APRIL 2004 REVISED JUNE 2007
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD
ADDRESS
PRIORITY
Power-Up
External Reset
Watchdog
Flash Memory
WDTIFG
KEYV
(see Note 1)
Reset
0FFFEh
15, highest
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
(Non)maskable
0FFFCh
14
Timer_B3
TBCCR0 CCIFG0 (see Note 2)
Maskable
0FFFAh
13
Timer_B3
TBCCR1 CCIFG1, TBCCR2 CCIFG2,
TBIFG (see Notes 1 and 2)
Maskable
0FFF8h
12
Comparator_A
CAIFG
Maskable
0FFF6h
11
Watchdog Timer
WDTIFG
Maskable
0FFF4h
10
USART0 Receive
URXIFG0
Maskable
0FFF2h
9
USART0 Transmit
UTXIFG0
Maskable
0FFF0h
8
ADC12
ADC12IFG (see Notes 1 and 2)
Maskable
0FFEEh
7
Timer_A3
TACCR0 CCIFG0 (see Note 2)
Maskable
0FFECh
6
Timer_A3
TACCR1 CCIFG1 and TACCR2 CCIFG2,
TAIFG (see Notes 1 and 2)
Maskable
0FFEAh
5
I/O Port P1 (Eight Flags)
P1IFG.0 to P1IFG.7 (see Notes 1 and 2)
Maskable
0FFE8h
4
DAC12
DMA
DAC12.0IFG, DAC12.1IFG,
DMA0IFG (see Notes 1 and 2)
Maskable
0FFE6h
3
0FFE4h
2
I/O Port P2 (Eight Flags)
P2IFG.0 to P2IFG.7 (see Notes 1 and 2)
Maskable
0FFE2h
1
Basic Timer1
BTIFG
Maskable
0FFE0h
0, lowest
NOTES:
1. Multiple source flags
2. Interrupt flags are located in the module.
3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot
disable it.
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