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| 型號(hào)： | MSP430C1351IPM |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 8 MHz, RISC MICROCONTROLLER, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁(yè)數(shù)： | 33/35頁(yè) |
| 文件大?。?/td> | 530K |
| 代理商： | MSP430C1351IPM |
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MSP430C13x1
MIXED SIGNAL MICROCONTROLLER
SLAS341B SEPTEMBER 2001 REVISED SEPTEMBER 2004
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External reset
Watchdog
WDTIFG
(see Note 1)
Reset
0FFFEh
15, highest
NMI
Oscillator fault
NMIIFG (see Notes 1 & 4)
OFIFG (see Notes 1 & 4)
(Non)maskable
0FFFCh
14
Timer_B3
TBCCR0 CCIFG
(see Note 2)
Maskable
0FFFAh
13
Timer_B3
TBCCR1 and TBCCR2
CCIFGs, TBIFG
(see Notes 1 & 2)
Maskable
0FFF8h
12
Comparator_A
CAIFG
Maskable
0FFF6h
11
Watchdog timer
WDTIFG
Maskable
0FFF4h
10
USART0 receive
URXIFG0
Maskable
0FFF2h
9
USART0 transmit
UTXIFG0
Maskable
0FFF0h
8
0FFEEh
7
Timer_A3
TACCR0 CCIFG
(see Note 2)
Maskable
0FFECh
6
Timer_A3
TACCR1 and TACCR2
CCIFGs, TAIFG
(see Notes 1 & 2)
Maskable
0FFEAh
5
I/O port P1 (eight flags)
P1IFG.0 to P1IFG.7
(see Notes 1 & 2)
Maskable
0FFE8h
4
0FFE6h
3
0FFE4h
2
I/O port P2 (eight flags)
P2IFG.0 to P2IFG.7
(see Notes 1 & 2)
Maskable
0FFE2h
1
0FFE0h
0, lowest
NOTES:
1. Multiple source flags
2. Interrupt flags are located in the module.
3. Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.
4. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disable
it.
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