參數(shù)資料
型號(hào)： MSP430C1351IPM
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 8 MHz, RISC MICROCONTROLLER, PQFP64
封裝： PLASTIC, QFP-64
文件頁(yè)數(shù)： 8/35頁(yè)
文件大?。?/td> 530K
代理商： MSP430C1351IPM
MSP430C13x1
MIXED SIGNAL MICROCONTROLLER
SLAS341B SEPTEMBER 2001 REVISED SEPTEMBER 2004
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
SCHMITT-trigger inputs Ports P1, P2, P3, P4, P5, and P6
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIT+
Positive-going input threshold voltage
VCC = 2.2 V
1.1
1.5
V
VIT+
Positive-going input threshold voltage
VCC = 3 V
1.5
1.9
V
VIT
Negative-going input threshold voltage
VCC = 2.2 V
0.4
0.9
V
VIT
Negative-going input threshold voltage
VCC = 3 V
0.90
1.3
V
Vhys
Input voltage hysteresis (VIT+ VIT)
VCC = 2.2 V
0.3
1.1
V
Vhys
Input voltage hysteresis (VIT+ VIT)
VCC = 3 V
0.4
1
V
standard inputs RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIL
Low-level input voltage
VCC = 2.2 V / 3 V
VSS
VSS+0.6
V
VIH
High-level input voltage
VCC = 2.2 V / 3 V
0.8
×VCC
VCC
V
input frequency Ports P1, P2, P3, P4, P5, and P6
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f(IN)
t(h) = t(L)
VCC = 2.2 V
8
MHz
t(h) = t(L)
VCC = 3 V
10
MHz
capture timing _ Timer_A3: TA0, TA1, TA2; Timer_B3: TB0, TB1, TB2
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Ports P2, P4:
VCC = 2.2 V/3 V
1.5
Cycle
t(int)
Ports P2, P4:
External trigger signal for the interrupt flag (see Notes 1 and 2)
VCC = 2.2 V
62
ns
t(int)
External trigger signal for the interrupt flag (see Notes 1 and 2)
VCC = 3 V
50
ns
NOTES:
1. The external signal sets the interrupt flag every time t(int) is met. It may be set even with trigger signals shorter than t(int).
The conditions to set the flag must be met independently of this timing constraint. t(int) is defined in MCLK cycles.
2. The external signal needs additional timing because of the maximum input-frequency constraint.
external interrupt timing
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Ports P1, P2:
VCC = 2.2 V/3 V
1.5
Cycle
t(int)
Ports P1, P2:
External trigger signal for the interrupt flag (see Notes 1 and 2)
VCC = 2.2 V
62
ns
t(int)
External trigger signal for the interrupt flag (see Notes 1 and 2)
VCC = 3 V
50
ns
NOTES:
1. The external signal sets the interrupt flag every time t(int) is met. It may be set even with trigger signals shorter than t(int).
The conditions to set the flag must be met independently of this timing constraint. t(int) is defined in MCLK cycles.
2. The external signal needs additional timing because of the maximum input-frequency constraint.
leakage current (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Ilkg(P1.x)
Leakage
current
Port P1
V(P1.x) (see Note 2)
VCC = 2.2 V/3 V
±50
nA
Ilkg(P2.x)
Leakage
current
Port P2
V(P2.3) V(P2.4) (see Note 2)
VCC = 2.2 V/3 V
±50
nA
NOTES:
1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The port pin must be selected as input and there must be no optional pullup or pulldown resistor.
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