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參數(shù)資料
| 型號： | MSP430C1351IPM |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 8 MHz, RISC MICROCONTROLLER, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁數(shù)： | 34/35頁 |
| 文件大?。?/td> | 530K |
| 代理商： | MSP430C1351IPM |
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MSP430C13x1
MIXED SIGNAL MICROCONTROLLER
SLAS341B SEPTEMBER 2001 REVISED SEPTEMBER 2004
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
special function registers
Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits
not allocated to a functional purpose are not physically present in the device. This arrangement provides simple
software access.
interrupt enable 1 and 2
76
5
4
0
UTXIE0
OFIE
WDTIE
32
1
rw-0
Address
0h
URXIE0
NMIIE
rw-0
WDTIE:
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog
Timer is configured in interval timer mode.
OFIE:
Oscillator-fault-interrupt enable
NMIIE:
Nonmaskable-interrupt enable
URXIE0:
USART0: UART and SPI receive-interrupt enable
UTXIE0:
USART0: UART and SPI transmit-interrupt enable
76
5
4
0
32
1
Address
01h
interrupt flag register 1 and 2
76
5
4
0
UTXIFG0
OFIFG
WDTIFG
32
1
rw-0
rw-1
rw-(0)
Address
02h
URXIFG0
NMIIFG
rw-1
rw-0
WDTIFG:
Set on Watchdog Timer overflow (in watchdog mode) or security key violation. Reset on VCC
power-up or a reset condition at RST/NMI pin in reset mode.
OFIFG:
Flag set on oscillator fault
NMIIFG:
Set via RST/NMI pin
URXIFG0: USART0: UART and SPI receive flag
UTXIFG0: USART0: UART and SPI transmit flag
76
5
4
0
32
1
Address
03h
module enable registers 1 and 2
76
5
4
0
UTXE0
32
1
rw-0
Address
04h
URXE0
USPIE0
URXE0:
USART0: UART receive enable
UTXE0:
USART0: UART transmit enable
USPIE0:
USART0: SPI (synchronous peripheral interface) transmit and receive enable
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