參數(shù)資料
型號: MSP430F249MPMEP
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PQFP64
封裝: GREEN, PLASTIC, QFP-64
文件頁數(shù): 22/81頁
文件大?。?/td> 1133K
代理商: MSP430F249MPMEP
MSP430F249-EP
MIXED SIGNAL MICROCONTROLLER
2008
29
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
outputs ports P1, P2, P3, P4, P5, and P6
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX
UNIT
IOH(max) = 1.5 mA, (see Note 1)
2.2 V
VCC 0.25
VCC
V
High level output voltage
IOH(max) = 6 mA, (see Note 2)
2.2 V
VCC 0.60
VCC
V
VOH
High-level output voltage
IOH(max) = 1.5 mA, (see Note 1)
3 V
VCC 0.25
VCC
V
IOH(max) = 6 mA, (see Note 2)
3 V
VCC 0.60
VCC
IOL(max) = 1.5 mA, (see Note 1)
2.2 V
VSS VSS + 0.25
V
Low level output voltage
IOL(max) = 6 mA, (see Note 2)
2.2 V
VSS VSS + 0.60
V
VOL
Low-level output voltage
IOL(max) = 1.5 mA, (see Note 1)
3 V
VSS VSS + 0.25
V
IOL(max) = 6 mA, (see Note 2)
3 V
VSS VSS + 0.60
NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the maximum
voltage drop specified.
2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to satisfy the maximum
voltage drop specified.
output frequency ports P1, P2, P3, P4, P5, and P6
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
f
Port output frequency
P1.4/SMCLK, CL = 20 pF, RL = 1 kW
2.2 V
DC
10
MHz
fPx.y
Port output frequency
with load
P1.4/SMCLK, CL = 20 pF, RL = 1 kW
(see Notes 1 and 2)
3 V
DC
12
MHz
f
Clock output frequency
P2.0/ACLK/CA2, P1.4/SMCLK, CL = 20 pF,
2.2 V
DC
12
MHz
fPort_CLK Clock output frequency
P2.0/ACLK/CA2, P1.4/SMCLK, CL = 20 pF,
RL = 1 kW (see Note 2)
3.3 V
DC
16
MHz
P1.0/TACLK/CAOUT, CL = 20 pF, LF mode
30
50
70
P1.0/TACLK/CAOUT, CL = 20 pF, XT1 mode
40
50
60
%
t
Duty cycle of output
P1.1/TA0, CL = 20 pF, XT1 mode
40
60
%
t(Xdc)
Duty cycle of output
frequency
P1.1/TA0, CL = 20 pF, DCO
50% 15 ns
50 50% + 15 ns
P1.4/SMCLK, CL = 20 pF, XT2 mode
40
60
%
P1.4/SMCLK, CL = 20 pF, DCO
50% 15 ns
50% + 15 ns
NOTES: 1. A resistive divider with 2 times 0.5 kW between VCC and VSS is used as load. The output is connected to the center tap of the divider.
2. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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