參數(shù)資料
型號(hào): MSP430F2618TGQWTEP
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PBGA113
封裝: PLASTIC, BGA-113
文件頁(yè)數(shù): 25/92頁(yè)
文件大?。?/td> 1215K
代理商: MSP430F2618TGQWTEP
MSP430F2618- EP
MIXED SIGNAL MICROCONTROLLER
SLAS632 -- DECEMBER 2008
31
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
standard inputs -- RST/NMI
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX
UNIT
VIL
Low-level input voltage
2.2 V/3 V
VSS
VSS+0.6
V
VIH
High-level input voltage
2.2 V/3 V
0.8VCC
VCC
V
outputs -- ports P1 through P8
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX
UNIT
IOH(max) = --1.5 mA (see Note 1)
2 2 V
VCC--0.25
VCC
V
High level output voltage
IOH(max) = --6 mA (see Note 2)
2.2 V
VCC--0.6
VCC
V
VOH
High-level output voltage
IOH(max) = --1.5 mA (see Note 1)
3 V
VCC--0.25
VCC
V
IOH(max) = --6 mA (see Note 2)
3 V
VCC--0.6
VCC
IOL(max) = 1.5 mA (see Note 1)
2 2 V
VSS VSS+0.25
V
Low level output voltage
IOL(max) = 6 mA (see Note 2)
2.2 V
VSS
VSS+0.6
V
VOL
Low-level output voltage
IOL(max) = 1.5 mA (see Note 1)
3 V
VSS VSS+0.25
V
IOL(max) = 6 mA (see Note 2)
3 V
VSS
VSS+0.6
NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed 12 mA to satisfy the maximum
voltage drop specified.
2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed 48 mA to satisfy the maximum
voltage drop specified.
output frequency -- ports P1 through P8
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
f
Port output frequency
P1.4/SMCLK, CL =20pF, RL =1kΩ
2.2 V
DC
10
MHz
fPx.y
Port output frequency
with load
P1.4/SMCLK, CL 20 pF, RL 1 kΩ
(see Notes 1 and 2)
3.0 V
DC
12
MHz
f
Clock output frequency
P2.0/ACLK/CA2, P1.4/SMCLK, CL =20pF
2.2 V
DC
12
MHz
fPort_CLK Clock output frequency
P2.0/ACLK/CA2, P1.4/SMCLK, CL 20 pF
(see Note 2)
3.3 V
DC
16
MHz
P5.6/ACLK, CL = 20 pF, LF mode
30
50
70
P5.6/ACLK, CL =20pF, XT1mode
40
50
60
%
t
Duty cycle of output
P5.4/MCLK, CL =20pF, XT1mode
40
60
%
t(Xdc)
Duty cycle of output
frequency
P5.4/MCLK, CL =20pF, DCO
50% -- 15 ns
50 50% + 15 ns
q
y
P1.4/SMCLK, CL =20pF, XT2mode
40
60
%
P1.4/SMCLK, CL = 20 pF, DCO
50% -- 15 ns
50% + 15 ns
NOTES: 1. A resistive divider with 2 times 0.5 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the divider.
2. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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