參數(shù)資料
型號： MSP430F2618TGQWTEP
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PBGA113
封裝： PLASTIC, BGA-113
文件頁數(shù)： 62/92頁
文件大?。?/td> 1215K
代理商： MSP430F2618TGQWTEP
MSP430F2618- EP
MIXED SIGNAL MICROCONTROLLER
SLAS632 -- DECEMBER 2008
65
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC linearity specifications (see Figure 41)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
Resolution
12-bit monotonic
12
bits
INL
Integral nonlinearity (see Note 1)
VREF =1.5 V
DAC12AMPx = 7, DAC12IR = 1
2.2 V
2 0
8 0
LSB
INL
Integral nonlinearity (see Note 1)
VREF =2.5 V
DAC12AMPx = 7, DAC12IR = 1
3V
2.0
8.0
LSB
DNL
Differential nonlinearity
VREF =1.5 V
DAC12AMPx = 7, DAC12IR = 1
2.2 V
0 4
1 0
LSB
DNL
Differential nonlinearity
(see Note 1)
VREF =2.5 V
DAC12AMPx = 7, DAC12IR = 1
3V
0.4
1.0
LSB
Offset voltage without calibration
VREF =1.5 V
DAC12AMPx = 7, DAC12IR = 1
2.2 V
21
EO
Offset voltage without calibration
(see Notes 1 and 2)
VREF =2.5 V
DAC12AMPx = 7, DAC12IR = 1
3V
21
mV
EO
Offset voltage with calibration
VREF =1.5 V
DAC12AMPx = 7, DAC12IR = 1
2.2 V
2 5
mV
Offset voltage with calibration
(see Notes 1 and 2)
VREF =2.5 V
DAC12AMPx = 7, DAC12IR = 1
3V
2.5
dE(O)/dT
Offset error temperature
coefficient (see Note 1)
2.2 V/3 V
30
V/C
E
Gain error (see Note 1)
VREF =1.5 V
2.2 V
3 50 % FSR
EG
Gain error (see Note 1)
VREF =2.5 V
3V
3.50
% FSR
dE(G)/dT
Gain temperature
coefficient (see Note 1)
2.2 V/3 V
10
ppm of
FSR/C
Ti
f
ff t
lib ti
DAC12AMPx = 2
100
tOffset Cal
Time for offset calibration
(see Note 3)
DAC12AMPx = 3, 5
2.2 V/3 V
32
ms
tOffset_Cal
(see Note 3)
DAC12AMPx = 4, 6, 7
2.2 V/3 V
6
ms
NOTES: 1. Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients “a” and
“b” of the first-order equation: y = a + b x. VDAC12_xOUT =EO +(1+EG) (VeREF+/4095) DAC12_xDAT, DAC12IR = 1.
2. The offset calibration works on the output operational amplifier. Offset calibration is triggered setting bit DAC12CALON.
3. The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with
DAC12AMPx = {0, 1}. The DAC12 module should be configured prior to initiating calibration. Port activity during calibration may affect
accuracy and is not recommended.
Positive
Negative
VR+
Gain Error
Offset Error
DAC Code
DAC VOUT
Ideal transfer
function
RLoad =
AVCC
CLoad = 100pF
2
DAC Output
Figure 41. Linearity Test Load Conditions and Gain/Offset Definition
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