參數(shù)資料
型號: MSP430F2618TGQWTEP
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PBGA113
封裝: PLASTIC, BGA-113
文件頁數(shù): 5/92頁
文件大小: 1215K
代理商: MSP430F2618TGQWTEP
MSP430F2618- EP
MIXED SIGNAL MICROCONTROLLER
SLAS632 -- DECEMBER 2008
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
memory organization
Memory
Main: interrupt vector
Size
Flash
116KB
0x0FFFF 0x0FFC0
Main: interrupt vector
Main: code memory
Flash
0x0FFFF -- 0x0FFC0
0x1FFFF -- 0x03100
RAM (total)
Extended
Mirrored
Size
8kB
0x030FF -- 0x01100
6kB
0x030FF -- 0x01900
2kB
0x018FF -- 0x01100
Information memory
Size
Flash
256 Byte
0x010FF -- 0x01000
Boot memory
Size
ROM
1KB
0x00FFF -- 0x00C00
RAM (mirrored at
0x18FF to 0x01100)
Size
2KB
0x009FF -- 0x00200
Peripherals
16-bit
8-bit
8-bit SFR
0x001FF -- 0x00100
0x000FF -- 0x00010
0x0000F -- 0x00000
bootstrap loader (BSL)
The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access
to the MSP430 memory via the BSL is protected by a user-defined password. For complete description of the
features of the BSL and its implementation, see the application report Features of the MSP430 Bootstrap
Loader, literature number SLAA089.
BSL Function
Pins
Data Transmit
H1 - P1.1
Data Receive
M3 - P2.2
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D
Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
D
Segments 0 to n may be erased in one step, or each segment may be individually erased.
D
Segments A to D can be erased individually, or as a group with segments 0 to n.
Segments A to D are also called information memory.
D
Segment A contains calibration data. After reset, segment A is protected against programming or erasing.
It can be unlocked, but care should be taken not to erase this segment if the calibration data is required.
D
Flash content integrity check with marginal read modes
peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User’s Guide, literature number
SLAU144.
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