參數(shù)資料
型號： MSX532-TB792
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 數(shù)字信號處理外設(shè)
英文描述： DSP-CROSSBAR SWITCH, PBGA792
封裝： TBGA-792
文件頁數(shù)： 20/61頁
文件大?。?/td> 726K
代理商： MSX532-TB792
MSX Family Datasheet
Fairchild Semiconductor
[Rev. 1.10] 3/21/02
27
3.5
AC Electrical Specifications
(TA = 0°C to 70°C, VDD = 3.3V ±10%)
Note – Refer to Figure 7 for AC test conditions.
Table 14
AC Electrical Specifications for MSX532 and MSX340
Symbol
Parameter
–20
Units
Min
Max
RDATA
NRZ Data Rate
150
Mb/s
fRIO
Registered Input/Output Clock Frequency
75
MHz
tW_RIO
Registered Clock Pulse Width, High or Low
2
ns
tS_RI
Registered Input Setup Time to Clock
3.5
ns
tS_RO
Registered Output Setup Time to Clock
9.5
ns
tH_RI
Registered Input Clock to Hold Data
0
ns
tH_RO
Registered Output Clock to Hold Data
0
ns
tCO_RO
Registered Output Clock to Data Out Valid
11
ns
tCO_RI
Registered Input Clock to Data Out Valid
24
ns
tPHL, tPLH
One Way Signal Propagation Delay, Fanout = 1
20
ns
tMC Delta
Additional Delay Per Output Multicast (MC) Mode
2
ns
tW+
Input Flow-through Positive Pulse Width
6
tW-
Input Flow-through Negative Pulse Width
6
tSK
Skew
2
ns
tPZH_IT,
tPZL_IT
Input Enable to Valid Data
20
ns
tPZH_OT,
tPZL_OT
Output Enable to Valid Data
7.5
ns
tPZH_OT,
tPZL_OT
Output Enable to High Z State
7.5
ns
tRC
RapidConfigure Clock Period
20
ns
tW+_RC
tW-_RC
RapidConfigure Clock Pulse Width
5
ns
tS_RC
RapidConfigure Address Setup to RC Clock
1
ns
tH_RC
RapidConfigure Address Hold Time to RC Clock
4
ns
tP_RC
Read Back Access Time
9
ns
tP_RD
RC_RDY to Readback Data
4
ns
tP_UD
Update of Crosspoint to Data Out
10
ns
fJTAG
JTAG Clock Frequency (TCK)
8
MHz
tW_JTAG
JTAG Clock Pulse Width (TCK) at 20 MHz Cycle
40
60
ns
tS_JTAG
JTAG Setup Time
4
ns
tH_JTAG
JTAG Hold Time
0
ns
tP_JTAG
JTAG Clock to Output Data Valid (TDO)
10
ns
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