參數(shù)資料
型號(hào)： MSX532-TB792
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 數(shù)字信號(hào)處理外設(shè)
英文描述： DSP-CROSSBAR SWITCH, PBGA792
封裝： TBGA-792
文件頁數(shù)： 45/61頁
文件大小： 726K
代理商： MSX532-TB792
Fairchild Semiconductor
[Rev. 1.10] 3/21/02
5
MSX Family Datasheet
Figures
Figure 1
MSX532 Functional Block Diagram .................................................................................................... 1
Figure 2
MSX Switch Matrix Diagram............................................................................................................... 7
Figure 3
MSX IOB Block Diagram .................................................................................................................... 8
Figure 4
MSX Switch Configuration Signals ................................................................................................... 12
Figure 5
MSX JTAG Architecture .................................................................................................................... 20
Figure 6
JTAG State Machine........................................................................................................................... 21
Figure 7
Test Circuit and Waveform Definition ............................................................................................... 28
Figure 8
Registered Input and Registered Output Mode Timing (ICLK and OCLK Synchronized) ............... 28
Figure 9
Registered Input Timing Mode........................................................................................................... 28
Figure 10
Registered Output Timing Mode ........................................................................................................ 29
Figure 11
I/O Port Timing (Flow-through Mode)............................................................................................... 29
Figure 12
Input Enable Timing (Flow-through Mode) ....................................................................................... 29
Figure 13
Output Enable Timing ........................................................................................................................ 30
Figure 14
JTAG Timing ...................................................................................................................................... 30
Figure 15
RapidConfigure IOB or Crosspoint Read and Write Cycles .............................................................. 31
Figure 16
RapidConfigure Reset Command Cycle............................................................................................. 32
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