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參數(shù)資料
| 型號： | MT18JSF25672AY-1G1D1 |
| 元件分類： | DRAM |
| 英文描述： | 256M X 72 DDR DRAM MODULE, DMA240 |
| 封裝： | UDIMM-240 |
| 文件頁數(shù)： | 14/19頁 |
| 文件大小： | 644K |
| 代理商： | MT18JSF25672AY-1G1D1 |
PDF: 09005aef83606b46/Source: 09005aef83606afe
Micron Technology, Inc., reserves the right to change products or specifications without notice.
JSF18C256x72AZ.fm - Rev. A 9/08 EN
4
2008 Micron Technology, Inc. All rights reserved
2GB (x72, ECC, DR) 240-Pin DDR3 SDRAM UDIMM
Pin Assignments and Descriptions
Table 5:
Pin Descriptions
Symbol
Type
Description
2GB
A[13:0]
Input
Address inputs: Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 is sampled during a PRECHARGE
command to determine whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BA[2:0]) or all banks (A10 HIGH). If only one bank is to be precharged, the
bank is selected by BA. A12 is also used for BC4/BL8 identification as “BL on-the-fly”
during CAS commands. The address inputs also provide the op-code during the mode
register command set.
BA[2:0]
Input
Bank address inputs: BA[2:0] define the device bank to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register
(MR0, MR1, MR2, and MR3) is loaded during the LOAD MODE command.
CK0, CK0#,
CK1, CK1#
Input
Clock: CK and CK# are differential clock inputs. All control, command, and address input
signals are sampled on the crossing of the positive edge of CK and the negative edge of
CK#.
CKE[1:0]
Input
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DRAM.
DM[8:0]
Input
Input data mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with the input data, during a write access. DM is sampled on
both edges of the DQS. Although the DM pins are input-only, the DM loading is
designed to match that of the DQ and DQS pins.
ODT[1:0]
Input
On-die termination: ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DRAM. When enabled in normal operation, ODT is
only applied to the following pins: DQ, DQS, DQS#, and DM. The ODT input will be
ignored if disabled via the LOAD MODE command.
RAS#, CAS#, WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
RESET#
Input
(LVCMOS)
Reset: RESET# is an active LOW CMOS input referenced to Vss. The RESET# input receiver
is a CMOS input defined as a rail-to-rail signal with DC HIGH
≥ 0.8 × Vdd and DC
LOW
≤ 0.2 × Vdd. RESET# assertion and deassertion are asynchronous. System
applications will most likely be unterminated, heavily loaded, and have very slow slew
rates. A slow slew rate receiver design is recommended along with implementing on-
chip noise filtering to prevent false triggering (RESET# assertion minimum pulse width is
100ns).
S#[1:0]
Input
Chip select: S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
SA[2:0]
Input
Serial address inputs: These pins are used to configure the temperature sensor/SPD
EEPROM address range on the I2C bus.
SCL
Input
Serial clock for temperature sensor/SPD EEPROM: SCL is used to synchronize the
communication to and from the temperature sensor/SPD EEPROM.
CB[7:0]
I/O
Check bits: Data used for ECC.
DQ[63:0]
I/O
Data input/output: Bidirectional data bus.
DQS[8:0],
DQS#[8:0]
I/O
Data strobe: DQS and DQS# are differential data strobes. Output with read data. Edge-
aligned with read data. Input with write data. Center-aligned with write data.
SDA
I/O
Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out
of the temperature sensor/SPD EEPROM on the module on the I2C bus.
EVENT#
Output
(open drain)
Temperature event: The EVENT# pin is asserted by the temperature sensor when
critical temperature thresholds have been exceeded.
Vdd
Supply
Power supply: 1.5V ±0.075V. The component Vdd and VddQ are connected to the
module Vdd.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT18JSF25672AY-1G1D1 TR | 制造商:Micron Technology Inc 功能描述:2GB 256MX72 DDR3 SDRAM MODULE PBF DIMM 1.5V NON BUF - Tape and Reel |
| MT18JSF25672AY-1G4D1 | 功能描述:MODULE DDR3 SDRAM 2GB 240-DIMM RoHS:是 類別:存儲卡，模塊 >> 存儲器 - 模塊 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 存儲器類型:SDRAM 存儲容量:1GB 速度:133MHz 特點:- 封裝/外殼:168-DIMM |
| MT18JSF25672AZ-1G4G1 | 功能描述:MODULE DDR3 SDRAM 2GB 240UDIMM RoHS:是 類別:存儲卡，模塊 >> 存儲器 - 模塊 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 存儲器類型:SDRAM 存儲容量:1GB 速度:133MHz 特點:- 封裝/外殼:168-DIMM |
| MT18JSF25672AZ-1G6G1 | 功能描述:MODULE DDR3 SDRAM 2GB 240UDIMM RoHS:是 類別:存儲卡，模塊 >> 存儲器 - 模塊 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 存儲器類型:SDRAM 存儲容量:1GB 速度:133MHz 特點:- 封裝/外殼:168-DIMM |
| MT18JSF25672PDY-1G1D1 TR | 制造商:Micron Technology Inc 功能描述:2GB 256MX72 DDR3 SDRAM MODULE PBF DIMM 1.5V REGISTERED - Tape and Reel |
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