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| 型號(hào)： | MT46V64M4 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 16 Meg x 4 x 4 banks DDR SDRAM(16M x 4 x 4組,雙數(shù)據(jù)速率同步動(dòng)態(tài)RAM) |
| 中文描述： | 16梅格× 4 × 4銀行DDR SDRAM內(nèi)存（1,600 × 4 × 4組，雙數(shù)據(jù)速率同步動(dòng)態(tài)RAM）的 |
| 文件頁數(shù)： | 17/69頁 |
| 文件大?。?/td> | 2410K |
| 代理商： | MT46V64M4 |
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17
256Mb: x4, x8, x16 DDR SDRAM
256Mx4x8x16DDR_B.p65
–
Rev. B; Pub. 7/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
256Mb: x4, x8, x16
DDR SDRAM
ADVANCE
READs
READ bursts are initiated with a READ command, as
shown in Figure 6.
The starting column and bank addresses are provided
with the READ command and auto precharge is either
enabled or disabled for that burst access. If auto precharge
is enabled, the row being accessed is precharged at the
completion of the burst. For the generic READ com-
mands used in the following illustrations, auto precharge
is disabled.
During READ bursts, the valid data-out element from
the starting column address will be available following
the CAS latency after the READ command. Each subse-
quent data-out element will be valid nominally at the
next positive or negative clock edge (i.e., at the next
crossing of CK and CK#). Figure 7 shows general timing
for each possible CAS latency setting. DQS is driven by
the DDR SDRAM along with output data. The initial
LOW state on DQS is known as the read preamble; the
LOW state coincident with the last data-out element is
known as the read postamble.
Upon completion of a burst, assuming no other
commands have been initiated, the DQs will go
High-Z. A detailed explanation of
t
DQSQ (valid data-out
skew),
t
QH (data-out window hold), the valid data win-
dow are depicted in Figure 27. A detailed explanation of
t
DQSCK (DQS transition skew to CK) and
t
AC (data-out
transition skew to CK) is depicted in Figure 28.
Data from any READ burst may be concatenated with
or truncated with data from a subsequent READ com-
mand. In either case, a continuous flow of data can be
maintained. The first data element from the new burst
follows either the last element of a completed burst or
the last desired data element of a longer burst which is
being truncated. The new READ command should be
issued
x
cycles after the first READ command, where
x
equals the number of desired data element pairs (pairs
are required by the 2
n
-prefetch architecture). This is
shown in Figure 8. A READ command can be initiated on
any clock cycle following a previous READ command.
Nonconsecutive read data is shown for illustration in
Figure 9. Full-speed random read accesses within a page
(or pages) can be performed as shown in Figure 10.
Figure 6
READ Command
CS#
WE#
CAS#
RAS#
CKE
CA
x4: A0
–
A9, A11
x8: A0
–
A9
x16: A0
–
A8
A10
BA0,1
HIGH
EN AP
DIS AP
BA
x4: A12
x8: A11, A12
x16: A9, A11, A12
CK
CK#
CA = Column Address
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Auto Precharge
DON
’
T CARE
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT46V64M4_1 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:Double Data Rate (DDR) SDRAM |
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