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參數(shù)資料
| 型號： | MT46V64M4 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 16 Meg x 4 x 4 banks DDR SDRAM(16M x 4 x 4組,雙數(shù)據(jù)速率同步動態(tài)RAM) |
| 中文描述： | 16梅格× 4 × 4銀行DDR SDRAM內(nèi)存（1,600 × 4 × 4組，雙數(shù)據(jù)速率同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 60/69頁 |
| 文件大?。?/td> | 2410K |
| 代理商： | MT46V64M4 |
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60
256Mb: x4, x8, x16 DDR SDRAM
256Mx4x8x16DDR_B.p65
–
Rev. B; Pub. 7/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
256Mb: x4, x8, x16
DDR SDRAM
ADVANCE
TIMING PARAMETERS
-7
-75
-8
SYMBOL
t
CH
t
CL
t
CK (2.5)
t
CK (2)
t
IH
MIN
0.45
0.45
7
7.5
1
MAX
0.55
0.55
12
12
MIN
0.45
0.45
7.5
10
1
MAX
0.55
0.55
12
2
MIN
0.45
0.45
8
10
1.1
MAX
0.55
0.55
12
12
UNITS
t
CK
t
CK
ns
ns
ns
INITIALIZE AND LOAD MODE REGISTERS
-7
-75
-8
SYMBOL
t
IS
t
MRD
t
RFC
t
RP
t
VTD
MIN
1
15
67
15
0
MAX
MIN
1
15
75
20
0
MAX
MIN
1.1
16
80
20
0
MAX
UNITS
ns
ns
ns
ns
ns
t
VTD
1
CKE
LVCMOS
LOW LEVEL
DQ
BA0, BA1
200 cycles of CK
3
Load Extended
Mode Register
Load Mode
Register
2
tMRD
tMRD
tRP
tRFC
tRFC
5
t
IS
Power-up: V
DD
and CK stable
T = 200μs
High-Z
t
IH
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DM
DQS
High-Z
A0-A9,
A11, A12
RA
A10
RA
ALL BANKS
CK
CK#
t
CH
t
CL
t
CK
V
TT
1
V
REF
V
DD
V
DD
Q
COMMAND
66
6
LMR
NOP
PRE
LMR
AR
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AR
ACT
5
tIS
tIH
BA1 = L
tIS
tIH
t
IS
t
IH
BA1 = L
tIS
tIH
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CODE
CODE
tIS
tIH
CODE
CODE
PRE
ALL BANKS
tIS
tIH
NOTE:
1. V
TT
is not applied directly to the device; however, tVTD should be greater than or equal to zero to avoid device latch-up.
V
DD
Q
,
V
TT,
and V
REF,
must be equal to or less than V
DD
+ 0.3V. Alternatively, V
TT
may be 1.35V maximum during power up, even if
V
DD
/V
DD
Q are 0 volts, provided a minimum of 42 ohms of series resistance is used between the V
TT
supply and the input pin.
2. Reset the DLL with A8 = H.
3. tMRD is required before any command can be applied, and 200 cycles of CK are required before a READ command can be issued.
4. The two AUTO REFRESH commands at Tc0 and Td0 may be applied after the LOAD MODE REGISTER (LMR) command at Ta0.
5. Although not required by the Micron device, JEDEC specifies issuing another LMR command (A8 = L) prior to activating any bank.
6. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE command, RA = Row
Address, BA = Bank Address
T0
T1
T2
Ta0
Tb0
Tc0
Td0
Te0
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DON
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T CARE
BA
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()()
()()
()()
()()
()()
()()
()()
()()
()()
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()()
()()
tRP
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MT46V64M4_1 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:Double Data Rate (DDR) SDRAM |
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