參數(shù)資料
型號(hào)： MT46V64M8
廠商： Micron Technology, Inc.
英文描述： 16 Meg x 8 x 4 banks DDR SDRAM(16M x 8 x 4組,雙數(shù)據(jù)速率同步動(dòng)態(tài)RAM)
中文描述： 16梅格× 8 × 4銀行DDR SDRAM內(nèi)存（1,600 × 8 × 4組，雙數(shù)據(jù)速率同步動(dòng)態(tài)RAM）的
文件頁(yè)數(shù)： 36/70頁(yè)
文件大?。?/td> 2524K
代理商： MT46V64M8
36
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_A.p65
–
Rev. A; Pub 10/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
512Mb: x4, x8, x16
DDR SDRAM
ADVANCE
Figure 24
WRITE to PRECHARGE
Odd Number of Data, Interrupting
t
DQSS
t
DQSS (NOM)
CK
CK#
COMMAND
WRITE
NOP
NOP
PRE
9
NOP
NOP
ADDRESS
Bank
a
,
Col
b
Bank,
(
a
or
all
)
NOP
T0
T1
T2
T3
T2n
T4
T5
NOTE
: 1. DI
b
= data-in for column
b
.
2. Subsequent element of data-in is applied in the programmed order following DI
b
.
3. An interrupted burst of 4 is shown; one data element is written.
4.tWR is referenced from the first positive CK edge after the last data-in pair.
5. The PRECHARGE and WRITE commands are to the same bank.
6. A10 is LOW with the WRITE command (auto precharge is disabled).
7. DQS is required at T1n, T2 and T2n (nominal case) to register DM.
8. If the burst of 8 was used, DM would be required at T3 and T3n and not at T4 and T4n because the PRECHARGE
command would mask the last two data elements.
9. PRE = PRECHARGE command.
T1n
T6
t
WR
t
RP
DQ
DQS
DM
DI
b
t
DQSS
t
DQSS (MIN)
DQ
DQS
DM
t
DQSS
t
DQSS (MAX)
DQ
DQS
DM
DI
b
DI
b
DON
’
T CARE
TRANSITIONING DATA
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