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參數(shù)資料
| 型號(hào)： | MT48LC2M32LFFC |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 512K x 32 x 4 banks 3.3v SDRAM(3.3V,512K x 32 x 4組同步動(dòng)態(tài)RAM) |
| 中文描述： | 為512k × 32 × 4銀行3.3V的內(nèi)存電壓（3.3V，512K采樣× 32 × 4組同步動(dòng)態(tài)RAM）的 |
| 文件頁數(shù)： | 35/50頁 |
| 文件大?。?/td> | 1054K |
| 代理商： | MT48LC2M32LFFC |
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35
64Mb: x32, 3.3V SDRAM
BatRam_3V.p65 – Rev. 0.7, Pub. 2/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
64Mb: x32, 3.3V
SDRAM
PRELIMINARY
INITIALIZE AND LOAD MODE REGISTER
*CAS latency indicated in parentheses.
NOTE:
1. The Mode Register may be loaded prior to the AUTO REFRESH cycles if desired.
2. If CS is HIGH at clock high time, all commands applied are NOP, with CKE a “ Don’t Care.”
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after command is issued.
-8
-10
SYMBOL*
t
CKH
t
CKS
t
CMH
t
CMS
t
MRD
3
t
RC
t
RP
MIN
1
2
1
2
2
80
20
MAX
MIN
1
2
1
2
2
100
20
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
TIMING PARAMETERS
-8
-10
SYMBOL*
t
AH
t
AS
t
CH
t
CL
t
CK (3)
t
CK (2)
t
CK (1)
MIN
1
2.5
3
3
8
13
25
MAX
MIN
1
2.5
3
3
10
13
25
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
tCH
tCL
tCK
CKE
CLK
COMMAND
DQ
BA0, BA1
BANK
tRCAR
tMRD
tRCAR
AUTO REFRESH
AUTO REFRESH
Program Mode Register
1, 2
tCMS
tCMH
Precharge
all banks
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tRP
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tCKS
Power-up:
V
DD
and
CK stable
T = 100μs
(MIN)
PRECHARGE
NOP
AUTO
REFRESH
NOP
LOAD MODE
REGISTER
ACTIVE
NOP
NOP
NOP
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AUTO
REFRESH
ALL
BANKS
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High-Z
tCKH
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DQM 0-3
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()()
()()
()()
()()
()()
NOP
(
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tCMS
tCMH
tCMS
tCMH
A0-A9
ROW
tAH
tAS
CODE
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A10
ROW
tAH
tAS
CODE
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ALL BANKS
SINGLE BANK
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DON’T CARE
UNDEFINED
T0
T1
Tn + 1
To + 1
Tp + 1
Tp + 2
Tp + 3
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