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參數(shù)資料
| 型號： | MT58L128L36D1T-5IT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 128K X 36 STANDARD SRAM, 2.8 ns, PQFP100 |
| 封裝： | PLASTIC, MS-026BHA, TQFP-100 |
| 文件頁數(shù)： | 17/23頁 |
| 文件大?。?/td> | 604K |
| 代理商： | MT58L128L36D1T-5IT |
3
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L256L18D1.p65 – Rev 12/99
1999, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
PRELIMINARY
GENERAL DESCRIPTION (continued)
Asynchronous inputs include the output enable
(OE#), clock (CLK) and snooze enable (ZZ). There is also
a burst mode input (MODE) that selects between inter-
leaved and linear burst modes. The data-out (Q), en-
abled by OE#, is also asynchronous. WRITE cycles can
be from one to two bytes wide (x18) or from one to four
bytes wide (x32/x36), as controlled by the write control
inputs.
Burst operation can be initiated with either address
status processor (ADSP#) or address status controller
(ADSC#) inputs. Subsequent burst addresses can be
internally generated as controlled by the burst advance
input (ADV#).
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During WRITE cycles on the x18 device,
BWa# controls DQa’s and DQPa; BWb# controls DQb’s
and DQPb. During WRITE cycles on the x32 and x36
devices, BWa# controls DQa’s and DQPa; BWb# con-
trols DQb’s and DQPb; BWc# controls DQc’s and DQPc;
BWd# controls DQd’s and DQPd. GW# LOW causes all
bytes to be written. Parity bits are only available on the
x18 and x36 versions.
This device incorporates an additional pipelined
enable register which delays turning off the output
buffer an additional cycle when a deselect is executed.
This feature allows depth expansion without penaliz-
ing system performance.
Micron’s 4Mb SyncBurst SRAMs operate from a
+3.3V VDD power supply, and all inputs and outputs are
TTL-compatible. The device is ideally suited for
Pentium and PowerPC pipelined systems and systems
that benefit from a very wide, high-speed data bus. The
device is also ideal in generic 16-, 18-, 32-, 36-, 64- and
72-bit-wide applications.
*No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
**Pins 43 and 42 are reserved for address expansion, 8Mb and 16Mb respectively.
TQFP PIN ASSIGNMENT TABLE
PIN #
x18
x32/x36
1
NC
NC/DQPc*
2
NC
DQc
3
NC
DQc
4
VDDQ
5
VSS
6
NC
DQc
7
NC
DQc
8
DQb
DQc
9
DQb
DQc
10
VSS
11
VDDQ
12
DQb
DQc
13
DQb
DQc
14
VDD
15
VDD
16
NC
17
VSS
18
DQb
DQd
19
DQb
DQd
20
VDDQ
21
VSS
22
DQb
DQd
23
DQb
DQd
24
DQPb
DQd
25
NC
DQd
PIN #
x18
x32/x36
PIN #
x18
x32/x36
PIN #
x18
x32/x36
26
VSS
27
VDDQ
28
NC
DQd
29
NC
DQd
30
NC
NC/DQPd*
31
MODE
32
SA
33
SA
34
SA
35
SA
36
SA1
37
SA0
38
DNU
39
DNU
40
VSS
41
VDD
42
NF**
43
NF**
44
SA
45
SA
46
SA
47
SA
48
SA
49
SA
50
SA
76
VSS
77
VDDQ
78
NC
DQb
79
NC
DQb
80
SA
NC/DQPb*
81
SA
82
SA
83
ADV#
84
ADSP#
85
ADSC#
86
OE#
87
BWE#
88
GW#
89
CLK
90
VSS
91
VDD
92
CE2#
93
BWa#
94
BWb#
95
NC
BWc#
96
NC
BWd#
97
CE2
98
CE#
99
SA
100
SA
51
NC
NC/DQPa*
52
NC
DQa
53
NC
DQa
54
VDDQ
55
VSS
56
NC
DQa
57
NC
DQa
58
DQa
59
DQa
60
VSS
61
VDDQ
62
DQa
63
DQa
64
ZZ
65
VDD
66
NC
67
VSS
68
DQa
DQb
69
DQa
DQb
70
VDDQ
71
VSS
72
DQa
DQb
73
DQa
DQb
74
DQPa
DQb
75
NC
DQb
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT58L128L36F1 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH SYNCBURST SRAM |
| MT58L128L36F1T-10 | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Quad 3.3V 4M-Bit 128K x 36 10ns 100-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT58L128L36F1T-10 TR | 制造商:Cypress Semiconductor 功能描述:128KX36 SRAM PLASTIC TQFP 3.3V |
| MT58L128L36F1T-8.5 | 制造商:Cypress Semiconductor 功能描述:128KX36 SRAM PLASTIC TQFP 3.3V 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT58L128L36F1T-8.5C | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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