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參數(shù)資料
| 型號： | MT58L32L36PT-7.5 |
| 元件分類： | SRAM |
| 英文描述： | 32K X 36 CACHE SRAM, 4.2 ns, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 1/18頁 |
| 文件大?。?/td> | 354K |
| 代理商： | MT58L32L36PT-7.5 |
1
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Pipelined, SCD SyncBurst SRAM
2002, Micron Technology, Inc.
MT58L64L18P_B.p65 – Rev. B, Pub. 11/02
1Mb: 64K x 18, 32K x 32/36
3.3V I/O, PIPELINED, SCD SYNCBURST SRAM
NOT RECOMENDED FOR NEW DESIGNS
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
FEATURES
Fast clock and OE# access times
Single +3.3V +0.3V/-0.165V power supply (VDD)
Separate +3.3V +0.3V/-0.165V isolated output
buffer supply (VDDQ)
SNOOZE MODE for reduced-power standby
Single-cycle deselect (Pentium BSRAM-
compatible)
Common data inputs and data outputs
Individual BYTE WRITE control and GLOBAL
WRITE
Three chip enables for simple depth expansion
and address pipelining
Clock-controlled and registered addresses, data
I/Os and control signals
Internally self-timed WRITE cycle
Burst control pin (interleaved or linear burst)
Automatic power-down for portable applications
100-lead TQFP for high density, high speed SRAMs
Low capacitive bus loading
x18, x32, and x36 options available
OPTIONS
MARKING
Timing (Access/Cycle/MHz)
3.5ns/6.0ns/166 MHz
-6
4.2ns/7.5ns/133 MHz
-7.5
5ns/10ns/100 MHz
-10
Configurations
64K x 18
MT58L64L18P
32K x 32
MT58L32L32P
32K x 36
MT58L32L36P
Package
100-pin TQFP
T
Operating Temperature Range
Commercial (0C to +70C)
None
Part Number Example:
MT58L64L18PT-10
MT58L64L18P, MT58L32L32P,
MT58L32L36P
3.3V VDD, 3.3V I/O, Pipelined, Single-
Cycle Deselect
through registers controlled by a positive-edge-trig-
gered single clock input (CLK). The synchronous in-
puts include all addresses, all data inputs, active LOW
chip enable (CE#), two additional chip enables for easy
depth expansion (CE2, CE2#), burst control inputs
(ADSC#, ADSP#, ADV#), byte write enables (BWx#) and
global write (GW#).
Asynchronous inputs include the output enable
(OE#), clock (CLK) and snooze enable (ZZ). There is
also a burst mode pin (MODE) that selects between
interleaved and linear burst modes. The data-out (Q),
enabled by OE#, is also asynchronous. WRITE cycles
can be from one to two bytes wide (x18) or from one to
four bytes wide (x32/x36), as controlled by the write
control inputs.
Burst operation can be initiated with either address
status processor (ADSP#) or address status controller
(ADSC#) input pins. Subsequent burst addresses can
be internally generated as controlled by the burst ad-
vance pin (ADV#).
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During WRITE cycles on the x18 device,
BWa# controls DQa pins and DQPa; BWb# controls DQb
pins and DQPb. During WRITE cycles on the x32 and
x36 devices, BWa# controls DQa pins and DQPa; BWb#
controls DQb pins and DQPb; BWc# controls DQc pins
GENERAL DESCRIPTION
The Micron SyncBurst SRAM family employs
high-speed, low-power CMOS designs that are fabri-
cated using an advanced CMOS process.
The MT58L64L18P and MT58L32L32/36P 1Mb
SRAMs integrate a 64K x 18, 32K x 32, or 32K x 36 SRAM
core with advanced synchronous peripheral circuitry
and a 2-bit burst counter. All synchronous inputs pass
*JEDEC-standard MS-026 BHA (LQFP).
100-Pin TQFP*
1Mb SYNCBURST
SRAM
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MT58L512L18D | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM |
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| MT58L512L18F | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:8Mb: 512K x 18, 256K x 32/36 FLOW-THROUGH SYNCBURST SRAM |
| MT58L512L18FF-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT58L512L18FF-10IT | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
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