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參數(shù)資料
| 型號(hào)： | MT58L32L36PT-7.5 |
| 元件分類： | SRAM |
| 英文描述： | 32K X 36 CACHE SRAM, 4.2 ns, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 4/18頁 |
| 文件大?。?/td> | 354K |
| 代理商： | MT58L32L36PT-7.5 |
12
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L64L18P_B.p65 – Rev. B, Pub. 11/02
2002, Micron Technology, Inc.
1Mb: 64K x 18, 32K x 32/36
3.3V I/O, PIPELINED, SCD SYNCBURST SRAM
NOT RECOMENDED FOR NEW DESIGNS
Q
50
V = 1.5V
Z = 50
O
T
Figure 1
Q
351
317
5pF
+3.3V
Figure 2
LOAD DERATING CURVES
Micron 64K x 18, 32K x 32, or 32K x 36 SyncBurst
SRAM timing is dependent upon the capacitive load-
ing on the outputs.
Consult the factory for copies of I/O current versus
voltage curves.
AC TEST CONDITIONS
Input pulse levels ................. VIH = (VDD/2.2) + 1.5V
.................... VIL = (VDD/2.2) - 1.5V
Input rise and fall times ..................................... 1ns
Input timing reference levels ..................... VDD/2.2
Output reference levels ............................ VDDQ/2.2
Output load ............................. See Figures 1 and 2
Output Load Equivalent
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