參數(shù)資料
型號: MT58L32L36PT-7.5
元件分類: SRAM
英文描述: 32K X 36 CACHE SRAM, 4.2 ns, PQFP100
封裝: PLASTIC, TQFP-100
文件頁數(shù): 18/18頁
文件大小: 354K
代理商: MT58L32L36PT-7.5
9
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L64L18P_B.p65 – Rev. B, Pub. 11/02
2002, Micron Technology, Inc.
1Mb: 64K x 18, 32K x 32/36
3.3V I/O, PIPELINED, SCD SYNCBURST SRAM
NOT RECOMENDED FOR NEW DESIGNS
ABSOLUTE MAXIMUM RATINGS*
Voltage on VDD Supply Relative to VSS .... -0.5V to +4.6V
Voltage on VDDQ Supply
Relative to VSS .................................... -0.5V to +4.6V
VIN -0.5V to VDDQ + 0.5V
Storage Temperature (plastic) ........... -55C to +150C
Junction Temperature** ..................................... +150C
Short Circuit Output Current .............................. 100mA
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
**Maximum junction temperature depends upon
package type, cycle time, loading, ambient tempera-
ture and airflow. See Micron Technical Note TN-05-14
for more information.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0C
≤ T
A ≤ +70C; VDD, VDDQ = +3.3V +0.3V/-0.165V unless otherwise noted)
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
Input High (Logic 1) Voltage
VIH
2.0
VDD + 0.3
V
1, 2
Input Low (Logic 0) Voltage
VIL
-0.3
0.8
V
1, 2
Input Leakage Current
0V
≤ VIN ≤ VDD
ILI
-1.0
1.0
A
3
Output Leakage Current
Output(s) disabled,
ILO
-1.0
1.0
A
0V
≤ VIN ≤ VDD
Output High Voltage
IOH = -4.0mA
VOH
2.4
V
1, 4
Output Low Voltage
IOL = 8.0mA
VOL
0.4
V
1, 4
Supply Voltage
VDD
3.135
3.6
V
1
Isolated Output Buffer Supply
VDDQ
3.135
VDD
V
1, 5
NOTE: 1. All voltages referenced to VSS (GND).
2. Overshoot:
VIH
≤ +4.6V for t ≤ tKC/2 for I ≤ 20mA
Undershoot:
VIL
-0.7V for t
tKC/2 for I ≤ 20mA
Power-up:
VIH
≤ +3.6V and VDD ≤ 3.135V for t ≤ 200ms
3. MODE pin has an internal pull-up, and input leakage = ±10A.
4. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the shown DC values. AC I/O
curves are available upon request.
5. VDDQ should never exceed VDD. VDD and VDDQ can be connected together.
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