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參數(shù)資料
| 型號(hào)： | MT58L512L18DT-10IT |
| 元件分類： | SRAM |
| 英文描述： | 512K X 18 CACHE SRAM, 5 ns, PQFP100 |
| 封裝： | PLASTIC, MS-026BHA, TQFP-100 |
| 文件頁數(shù)： | 30/31頁 |
| 文件大?。?/td> | 613K |
| 代理商： | MT58L512L18DT-10IT |
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8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L512L18D_C.p65 – Rev. 6/01
2001, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
3.3V I/O, PIPELINED, DCD SYNCBURST SRAM
TQFP PIN DESCRIPTIONS (CONTINUED)
x18
x32/x36
SYMBOL
TYPE
DESCRIPTION
84
ADSP#
Input
Synchronous Address Status Processor: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ is performed using the new address,
independent of the byte write enables and ADSC#, but dependent
upon CE#, CE2 and CE2#. ADSP# is ignored if CE# is HIGH. Power-
down state is entered if CE2 is LOW or CE2# is HIGH.
85
ADSC#
Input
Synchronous Address Status Controller: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ or WRITE is performed using the new address if
CE# is LOW. ADSC# is also used to place the chip into power-down
state when CE# is HIGH.
31
MODE
Input
Mode: This input selects the burst sequence. A LOW on this pin
selects “l(fā)inear burst.” NC or HIGH on this pin selects “interleaved
burst.” Do not alter input state while device is operating.
(a) 58, 59,
(a) 52, 53,
DQa
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is DQa pins; Byte “b”
62, 63, 68, 69, 56-59, 62, 63
Output is DQb pins. For the x32 and x36 versions, Byte “a” is DQa pins;
72, 73
Byte “b” is DQb pins; Byte “c” is DQc pins; Byte “d” is DQd pins.
(b) 8, 9, 12,
(b) 68, 69
DQb
Input data must meet setup and hold times around the rising edge
13, 18, 19, 22, 72-75, 78, 79
of CLK.
23
(c) 2, 3, 6-9,
DQc
12, 13
(d) 18, 19,
DQd
22-25, 28, 29
74
51
NF/DQPa
NF/
No Function/Parity Data I/Os: On the x32 version, these pins are No
24
80
NF/DQPb
I/O
Function (NF). On the x18 version, Byte “a” parity is DQPa; Byte “b”
–
1
NF/DQPc
parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte
–
30
NF/DQPd
“b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd.
14, 15, 41, 65, 14, 15, 41, 65,
VDD
Supply Power Supply: See DC Electrical Characteristics and Operating
91
Conditions for range.
4, 11, 20, 27,
VDDQ
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and
54, 61, 70, 77 54, 61, 70, 77
Operating Conditions for range.
5, 10, 17, 21,
VSS
Supply Ground: GND.
26, 40, 55, 60, 26, 40, 55, 60,
67, 71, 76, 90 67, 71, 76, 90
38, 39
DNU
–
Do Not Use: These signals may either be unconnected or wired to
GND to improve package heat dissipation.
1-3, 6, 7,
16, 66
NC
–
No Connect: These signals are not internally connected and may be
16, 25, 28-30,
connected to ground to improve package heat dissipation.
51-53, 56, 57,
66, 75, 78, 79,
95, 96
42
NF
–
No Function: These pins are internally connected to the die and
43 (T Version) 43 (T Version)
have the capacitance of an input pin. It is allowable to leave these
pins unconnected or driven by signals. On the S Version, pin 42 is
reserved as an address upgrade pin for the 16Mb SyncBurst SRAM.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT58L512L18DT-7.5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT58L512L18F | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:8Mb: 512K x 18, 256K x 32/36 FLOW-THROUGH SYNCBURST SRAM |
| MT58L512L18FF-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT58L512L18FF-10IT | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT58L512L18FF-7.5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
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