參數(shù)資料
型號： MT9074
廠商： Mitel Networks Corporation
英文描述： T1/E1/J1 Single Chip Transceiver(T1/E1/J1單片收發(fā)器)
中文描述： T1/E1/J1收發(fā)單芯片收發(fā)器（T1/E1/J1收發(fā)單片收發(fā)器）
文件頁數(shù)： 100/120頁
文件大?。?/td> 362K
代理商： MT9074
MT9074
Advance Information
100
Bit
Name
Functional Description
7
ADREC
When high this bit will enable
address
recognition.
forces the receiver to recognize
only those packets having the
unique address as programmed
in
the
Receive
Recognition Registers or if the
address is an All call address.
This
Address
6
RxEN
When low this bit will disable
the
HDLC
receiver will disable after the
rest of the packet presently
being received is finished. The
receiver
internal
disabled.
When high the receiver will be
immediately enabled and will
begin searching for flags, Go-
aheads etc.
receiver.
The
clock
is
5
TxEN
When low this bit will disable
the HDLC transmitter. The
transmitter will disable after the
completion
of
presently being transmitted.
The transmitter internal clock is
disabled.
When high the transmitter will
be immediately enabled and
will begin transmitting data, if
any, or go to a mark idle or
interframe time fill state.
the
packet
4
EOP
Forms a tag on the next byte
written the TX FIFO, and when
set will indicate an end of
packet byte to the transmitter,
which will transmit an FCS
following
this
facilitates loading of multiple
packets into TX FIFO. Reset
automatically after a write to the
TX FIFO occurs.
byte.
This
3
FA
Forms a tag on the next byte
written to the TX FIFO, and
when set will indicate to the
transmitter that it should abort
the packet in which that byte is
being
transmitted.
automatically after a write to the
TX FIFO.
Reset
Table 144 - HDLC Control register 1
(Page B & C, Address 13H)
2
Mark-Idle
When low, the transmitter will
be in an idle state. When high it
is in an interframe time fill state.
These two states will only occur
when the TX FIFO is empty.
1
TR
When high this bit will enable
transparent mode. This will
perform the parallel to serial
conversion without inserting or
deleting zeros. No CRC bytes
are sent or monitored nor are
flags or aborts. A falling edge of
TxEN for transmit and a falling
edge of RxEN for receive is
necessary
transparent mode. This will also
synchronize the data to the
transmit and receive channel
structure. Also, the transmitter
must
be
enabled
control
register
transparent mode is entered.
to
initialize
through
before
1
0
FRUN
When high the HDLC TX and
RX are continuously enabled
providing the RxEN and TxEN
bits are set
Bit
Name
Functional Description
Table 144 - HDLC Control register 1
(Page B & C, Address 13H)
相關PDF資料
PDF描述
MT9075B E1 Single Chip Transceiver
MT9075B E1 Single Chip Transceiver(E1單片收發(fā)器)
MT9075 E1 Single Chip Transceiver
MT9075A E1 Single Chip Transceiver
MT9075AL E1 Single Chip Transceiver
相關代理商/技術參數(shù)
參數(shù)描述
MT9074_05 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/J1 Single Chip Transceiver
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