參數(shù)資料
型號： MT9074
廠商： Mitel Networks Corporation
英文描述： T1/E1/J1 Single Chip Transceiver(T1/E1/J1單片收發(fā)器)
中文描述： T1/E1/J1收發(fā)單芯片收發(fā)器（T1/E1/J1收發(fā)單片收發(fā)器）
文件頁數(shù)： 49/120頁
文件大?。?/td> 362K
代理商： MT9074
Advance Information
MT9074
49
3
BPVIM
Bipolar
Mask
.
interrupt is initiated whenever a
bipolar
violation
B8ZS encoding) is encountered.
If 1- unmasked, 0 - masked.
Violation
When
Interrupt
unmasked
an
(excluding
2
PRBSIM
Psuedo
Sequence
Mask
.
interrupt will be generated upon
detection of an error with a
channel
selected
testing. 1 - unmasked, 0 -
masked.
Random
Error
unmasked
Bit
Interrupt
When
an
for
PRBS
1
PDVIM
Pulse
Interrupt
unmasked
triggered whenever a sequence
of excessive consecutive zeros
is received on the line, or the
incoming pulse density is less
than N ones in a time frame of
8(N+1) where N = 1 to 23. If 1 -
unmasked, 0 - masked.
Density
Mask
.
an
Violation
When
interrupt
is
0
- - -
Unused
.
Bit
Name
Functional Description
7
FEOM
Framing Bit Error Counter
Overflow Interrupt Mask
.
When unmasked an interrupt
is initiated whenever the
framing bit error counter
changes from FFH to 00H. If
1 - unmasked, 0 - masked.
6
CRCOM
CRC-6
Overflow Interrupt Mask.
When unmasked an interrupt
is initiated whenever the
CRC-6
error
changes from FFH to 00H. If
1 - unmasked, 0 - masked.
Error
Counter
counter
Table 34 - Interrupt Mask Word Two (T1)
(Page 1, Address 1DH)
Bit
Name
Functional Description
Table 33 - Interrupt Mask Word One (T1)
(Page 1, Address 1CH
5
OOFOM
Out Of Frame Counter
Overflow Interrupt Mask
.
When unmasked an interrupt
is initiated whenever the out
of frame counter changes
state from changes from
FFH to 00H. If 1 - unmasked,
0 - masked.
4
COFAOM
Change
Alignment
Overflow Interrupt Mask
.
When unmasked an interrupt
is initiated whenever the
change of frame alignment
counter changes from FFH
to 00H. If 1 - unmasked, 0 -
masked.
of
Frame
Counter
3
BPVOM
Bipolar Violation Counter
Overflow Interrupt Mask
.
When unmasked an interrupt
is initiated whenever the
bipolar
violation
changes from FFH to 00H. If
1- unmasked, 0 - masked.
counter
2
PRBSOM
Psuedo
Sequence Error Counter
Overflow Interrupt Mask
.
When unmasked an interrupt
will be generated whenever
the PRBS error counter
changes from FFH to 00H. If
1 - unmasked, 0 - masked.
Random
Bit
1
PRBSMFOM
Psuedo
Sequence
Counter
Interrupt
unmasked an interrupt will
be generated whenever the
multiframe counter attached
to the PRBS error counter
overflows. FFH to 00H. If 1 -
unmasked, 0 - masked.
Random
Bit
Multiframe
Overflow
Mask
.
When
0
MFOOFOM
Multiframes Out Of Sync
Overflow Interrupt Mask.
When unmasked an interrupt
will be generated when the
multiframes out of frame
counter changes from FFH
to 00H. If 1 - unmasked, 0 -
masked.
Bit
Name
Functional Description
Table 34 - Interrupt Mask Word Two (T1)
(Page 1, Address 1DH)
相關PDF資料
PDF描述
MT9075B E1 Single Chip Transceiver
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