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參數(shù)資料
| 型號： | MT90883 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | TDM to Packet Processors |
| 中文描述： | TDM到分組處理器 |
| 文件頁數(shù)： | 51/97頁 |
| 文件大?。?/td> | 702K |
| 代理商： | MT90883 |
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MT90880/1/2/3
Data Sheet
51
Zarlink Semiconductor Inc.
Jitter Buffer Underrun
The jitter buffer will "underrun", i.e. empty completely under the following circumstances:
If the TDM data is played out of the TDM interfaces faster than the original TDM interface
If the packet delay variation in the network is larger than the programmed jitter buffer
If a large number of packets are lost in the network
Either condition will have the effect that packets will arrive too late to be played out at the correct time, with the TDM
interface being starved of data. When an underrun occurs, the TDM interface plays out "underrun data" for an
integer number of TDM frames. Underrun data can either be the last value played out on that timeslot, or a
pre-programmed value (e.g., 0xFF). When the late packet arrives, it is played out as normal.
The net effect depends on the cause of the underrun. If the interface is underrunning because of a difference in
frequency between the TDM clocks at either end of the network, the underrun introduces a frame slip every few
frames, depending on the size of the frequency discrepancy. For example, if the frequency difference was 50 ppm,
the frame slip will occur every 20,000 frames. The overall latency of the system will stay the same.
If the underrun is being caused by a large PDV in the network, the depth of the jitter buffer (and hence the overall
latency) for the underrunning context is increased by the number of frames that the packet is late. Over time, the
buffer depth will increase to match the peak PDV in the network.
The context descriptor protocol used by the MT9088x family has no sequencing information, so the device cannot
tell when packets are lost in the network. When a packet is lost, it makes the next arriving packet look like a "late"
packet. The next arriving packet is played out as soon as it arrives. This has the effect of reducing the jitter buffer
depth. If enough packets are lost, this will start to cause underruns in the device, until the buffer depth is built back
up to match the network PDV again.
Jitter buffer depth limitation
Packet delay variation in the network varies with time. As described above, the jitter buffer in the MT9088x
family will track the peak level of PDV in the network. However, it will only track the PDV upwards. If there is a
transient burst of activity in the network, the PDV may rise for a short period, and then settle back down again,
but the buffer depth will remain at the level required to handle the peak PDV.
For instance, if there was a link failure somewhere in the network, it could result in a large backlog of packets
being stored up at a network node. When the link is restored, these packets may be released suddenly, creating
a rush of very late packets. These packets will build up a large jitter buffer and a consequent increase in end to
end latency. This may be undesirable in applications that are sensitive to the increased latency.
The MT9088x provides a "drop threshold" limiting the maximum size of the queue to each context. When the
queue depth reaches the drop threshold, any further packets arriving are discarded, preventing the size of the
buffer and hence the end to end latency from increasing further.
Different applications have different requirements for where to set the drop thresholds. Applications such as
packet backplanes generally operate with tightly controlled networks with only a small variation packet delay.
Therefore the drop thresholds for this type of application need to be small, and the MT9088x allows the drop
thresholds to be set in increments of one packet, between 0 and 15 packets.
However, for applications such as circuit emulation, while end to end latency is still important, the network is
much larger and the packet delay variation cannot be as tightly controlled. Therefore the MT9088x provides a
second range, where the thresholds can be set to increment by steps of 16 packets, between 15 and 255
packets. Where a packet contains a single TDM frame of data, this represents a step size of 2 ms. The two
ranges are known as "backplane mode" and "network mode".
Jitter buffer overrun
The jitter buffer will "overrun", i.e., fill up completely under the following circumstances:
If the TDM data is played out of the TDM interfaces slower than the original TDM interface
If the packet delay variation in the network is larger than the programmed jitter buffer
相關PDF資料 |
PDF描述 |
|---|---|
| MT91600 | Programmable SLIC |
| MT91600AN | Programmable SLIC |
| MT91600AN1 | Programmable SLIC |
| MT91600ANR | Programmable SLIC |
| MT91600ANR1 | Programmable SLIC |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT90883A | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90883A/IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90883BP1N | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90883IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT9088IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
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