參數(shù)資料
型號: MT90883
廠商: Zarlink Semiconductor Inc.
英文描述: TDM to Packet Processors
中文描述: TDM到分組處理器
文件頁數(shù): 62/97頁
文件大小: 702K
代理商: MT90883
MT90880/1/2/3
Data Sheet
62
Zarlink Semiconductor Inc.
Fields from Packet Engine Control Register:
Table 26 - Control Register Fields for Example Traffic Class 3
Traffic Class 4: Ethernet - IPv4 - TCP - xxx
Configure the mask and match registers in the packet engine to control traffic to the CPU.
Flags
Mask
Fragment Offset
Mask
Time to Live (TTL)
Mask
Protocol
Mask
Header Checksum
Mask
Source IP address
Mask
Destination IP address
Allow Match
Check the packet has the right IP address for external DSP
traffic.
Remainder of the header
Mask
Control Register Field
Value
Comment
CPU_SEL3
set to 0b1
Send packets to the CPU.
CPU_PRI3
set to 0b10
Send to queue 2.
Byte offset to Context Descriptor
Don't care
Not TDM traffic
Protocol Field
Mask
Match / Comment
Ethernet
Destination MAC address
Mask
If the MAC is programmed into promiscuous mode then
the destination MAC address must be matched,
Source MAC address
Mask
Length / Type field
Allow match
0x0800 (IP)
IPv4
Version
Allow match
0b0100
Internet Header Length (IHL)
Allow match
0d20
Type of Service (TOS)
Mask
Total Length
Mask
Table 27 - Pattern Matching for Example Traffic Class 4
Protocol Field
Mask
Match / Comment
Table 25 - Pattern Matching for Example Traffic Class 3 (continued)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90883A 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90883A/IG 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90883BP1N 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90883IG 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT9088IG 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors