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參數(shù)資料
| 型號： | MT92220 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 1023 Channel Voice Over IP/AAL2 Processor |
| 中文描述： | ATM NETWORK INTERFACE, PBGA608 |
| 封裝： | 31 X 31 MM, 2.50 MM HEIGHT, MS-034, EPBGA-608 |
| 文件頁數(shù)： | 31/210頁 |
| 文件大?。?/td> | 1536K |
| 代理商： | MT92220 |
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Data Sheet
MT92220
31
Zarlink Semiconductor Inc.
the primary port operates, the MT92220 can interface with the same external SAR in all modes with minimal
changes.
Cells received on the secondary UTOPIA port, as well as any cells received on the primary port when it is
configured to operate in ATM mode, navigate through the UTOPIA module to reach their final destination. To
multiplex and de-multiplex traffic, the UTOPIA module uses input and output FIFO to contain cells. All cells sent to
the module are written into 4-cell input FIFO, which not only buffers a small amount of data but also serves the
synchronization needs of the various network clocks. These cells are then passed by a look-up engine whose job is
determining the VC number, as well as whether they should be kept or discarded. Cells arriving from either of the
UTOPIA ports need to be looked-up. To do so, 2 look-up tables are mapped in the external SSRAM. To point to an
entry in the SSRAM, a combination of bits from the VPI and VCI is used. Each look-up table can contain up to 2^16
entries = 64K entries, so up to 16 bits of the header can be used for the address.
Once the look-up engine has determined the VC number to which the cell is destined, it writes it to the appropriate
output FIFO. The output FIFO are larger, since they are necessary to buffer the peaks that occur in traffic. The
output FIFO are 8 cells deep. From these output FIFO, AAL5 cells are sent to the RX link agent for reassembly.
On the input side (UTOPIA reception), the UTOPIA ports can be configured through registers to behave as PHY or
ATM layers on the UTOPIA bus, depending on which chip is being interfaced with. In addition, each port has an
individual enable bit which prevents all traffic from being received on that port. Each port detects the parity on the
UTOPIA bus and any parity error will be reported to registers. Finally, null cells can also be enabled or disabled on
a per-port basis and any cells containing null headers will be deleted if this feature is enabled. Null headers can be
identified under either UNI or NNI conditions.
On the output side (UTOPIA transmission), the ports can also be configured as PHY or ATM layers. The TX
interfaces can also be configured to operate in multi-PHY mode, meaning that they will only drive the port's
tx_d
,
tx_prty
and
tx_soc
pins if this port has been selected to drive data onto the UTOPIA bus. Note that multi-PHY
mode only applies when the port is configured to operate as a PHY layer.
The Look-Up Table (LUT) of the UTOPIA is the central element to the module's behavior. It analyzes every cell
received from one of the UTOPIA ports and determines where the cell goes. A cell coming from port A or B will first
have its header compared with match and mask fields which indicate what are the acceptable header values
coming from this port. The way the match and mask operate is that the mask indicates which bits of the header
must be fixed and which may take on any value. For all bits whose mask value is '1' (fixed), the match indicates
what this value must be. This method is applied bit-wise to the VPI and VCI portions of the header. Any cell not
meeting these criteria will be routed according to the
rx_normal_vc_dest
or
rx_oam_vc_dest
bits contained in
registers. These fields indicate, for cells whose header does not match, where they should be routed: once again,
these fields support unicast, multicast or broadcast routing of cells. Depending on the OAM bit of the header, either
rx_normal_vc_dest
or
rx_oam_vc_dest
will be used, to allow management cells to be routed differently from data
cells. The routing fields are different for each input port.
However, if this validation procedure is passed, the look-up engine uses a certain number of bits from the VPI and
VCI of the cell header to determine the look-up entry corresponding to the cell. The number of bits of VCI used is
determined by the
vci_n
field, which is unique per port and can be configured from 0 to the full 16 bits of header:
note that the bits used are always the lower bits of the VCI. The rest of the bits are taken from the low bits of the
VPI, up to the full size of the look-up table (anywhere from 2^10 entries to 2^16 entries). These bits are then
concatenated to form a look-up address offset, which is added to the look-up table's base address to form the
absolute address of the look-up entry. The information at this address then reveals whether the cell will be kept and
to which cell queue it belongs, as well as a VC number if it is AAL2 or AAL5. The routing can be performed
differently for normal and OAM cells: in a typical application, OAM cells will be routed to one of the raw cell queues,
while user cells will be sent to an AAL2 or AAL5 VC.
The format of the look-up table entries is described below:
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