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參數(shù)資料
| 型號： | MT92220 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 1023 Channel Voice Over IP/AAL2 Processor |
| 中文描述： | ATM NETWORK INTERFACE, PBGA608 |
| 封裝： | 31 X 31 MM, 2.50 MM HEIGHT, MS-034, EPBGA-608 |
| 文件頁數(shù)： | 87/210頁 |
| 文件大?。?/td> | 1536K |
| 代理商： | MT92220 |
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Data Sheet
MT92220
87
Zarlink Semiconductor Inc.
This is discussed in further detail in the TX TDM section. Note that the Total number of frames keeps its definition
regardless of the compression rate, so with ADPCM 16 kbps, 4 frames of data only come out to 1 byte. The
assembly process can generate one of 6 payload types for xxPCM packets: one for PCM, one for each ADPCM
compression rate, and one for CN packets. In the TX RTP header structure, the payload types are written in the
RTP header.
9.5.4
TX Silence Suppression Structure Base
The TX Silence Suppression Structure Base points to a structure that will be used to perform silence suppression
on the xxPCM channel carried over this connection. When its value is 0000h, it means that no silence suppression
will be done on this channel. Silence suppression cannot be used on channels carrying more than 1 bearer.
9.5.5
Extra Delay Frames
The Extra Delay Frames are also related to the silence suppression calculations: they indicate that the packet
assembly should not use the most recent xxPCM data to assemble its packet, but instead should back up by a
certain number of frames. This allows the silence suppression calculations on a block to be performed fully before
the data is sent in an IP packet, ensuring, for example, that there is no start-up delay between the moment that
voice begins again and the moment that packets start being sent again.
9.5.6
RTP Timestamp
The RTP timestamp sent in PCM packets is calculated in the following way: global timestamp corresponding to the
first byte in the packet + Timestamp Offset written in the structure. The global timestamp is fed to the assembly
module by the TX TDM and can either be a free-running counter within the chip or a value extracted from 4
time-slots on the TDM bus. See the TX TDM section for more information on sourcing the timestamp.
9.5.7
Circular Buffer Base Addresses
Finally, at the very end of the structure, are a certain number of Circular Buffer Base Addresses that indicate, for
each channel in the connection, where is the circular buffer associated to it. These addresses point to 512 byte
boundaries, which is the minimum size for any circular buffer, since the xxPCM data is only contained in the left byte
of the circular buffer. The buffers may be larger, in which case the lower bits of the base address will not be used:
the Buffer Size field indicates the size for all the circular buffers used by this connection.
9.6
HDLC Packets
HDLC and CPU-sourced packets are not payload-formatted by the TX connection structure. They are simply
packaged in the link, IP and UDP (or null) headers and transmitted as such. The assembly process, in addition to
encapsulating the payload in these protocols, may perform some RTP functions. The Sequence Number Insert bit
indicates whether the RTP sequence number should be generated by the structure or kept as it is in the payload.
The Timestamp Insert bit, which comes from the event queue and originated in the TX TDM for HDLC packets (or
was written in the descriptor by the CPU), indicates whether the timestamp from the packet should be used, or if it
should be added to the global chip timestamp before being sent. To ensure that the timestamp passes through
without any modifications set the Timestamp Insert bit to '0' and the Timestamp Offset to 0h as well.
By setting the Sequence Number Insert bit to '0' and making the timestamp transparent as described above,
non-RTP packets can also be sent through HDLC or the CPU port.
In AAL2, the first byte of an HDLC packet received from the H.110 bus or a CPU packet in external memory must
contain, in its 5 high bits, the UUI value to be transmitted in the AAL2 packet. This first byte will not be carried in the
AAL2 payload. The CID will be inserted directly from the assembly structure in HDLC, or will be written in the
descriptor for CPU packets. The LI and HEC will be calculated by the chip and inserted in the packet.
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