NCT7491
http://onsemi.com
15
Offset 64 Format
In Offset 64 mode the range of values monitored is 64癈
to 191.5癈 (as opposed to 64癈 to +127.5癈 in 2s
complement mode). To read the temperature in this format
the user must subtract 64 from the value returned from the
temperature register. Offset 64 mode is enabled by setting bit
0 if register 0x7C to zero.
Table 7. OFFSET64
Register Code
Temperature
0
64癈
32
32癈
64
0癈
100
36癈
255
191癈
Round Robin Temperature Measurement
The local and remote sensors are read in sequence in a
continuous loop when monitoring is enabled (setting bit 0 of
register 0x40). The user may decide which temperature
channels are included in the monitoring loop using bits
<2:0> in register 0x13.
" Setting <0> of register 0x13 includes the local channel
in the monitoring loop.
" Setting <1> of register 0x13 includes the remote1
channel in the monitoring loop.
" Setting <2> of register 0x13 includes the remote2
channel in the monitoring loop.
Any channel not required in an application should be
removed from the loop to reduce the overall monitoring
time. Voltage channels may also be selected for the
monitoring loop. See the Voltage Monitoring section for
more information.
Temperature Averaging
The number of samples over which the temperature
readings (and voltage readings) are averaged is set by bits
<7:6> of register 0x40. The options are:
" 4 samples per averaged reading, <7:6> = <00>
" 8 samples per averaged reading, <7:6> = <01>
" 16 samples per averaged reading, <7:6> = <10>
" 32 samples per averaged reading, <7:6> = <11>
Averaging can be disabled for temperature readings by
setting bit <4> of register 0x73.
Temperature Limits
Temperature limits can be set for each channel to detect an
out of limit condition. These registers are programmed in the
same format as the temperature reading, so if Offset64 mode
is enabled then these registers must be programmed in that
format,   otherwise   theay   are   programmed   as   2s
complement.
" Remote1 Low Limit register: 0x4E
" Remote1 High Limit register: 0x4F
" Local Low Limit register: 0x50
" Local High Limit register: 0x51
" Remote2 Low Limit register: 0x52
" Remote2 High Limit register: 0x53
Offset Registers
Offset errors can be introduced into the temperature
measurements by clock noise or when the thermal diode is
located away from the hot spot. To achieve the specified
accuracy on this channel, these offsets must be removed.
The offset value is stored as an 8bit, twos complement
value. The value in the offset register is added to, or
subtracted from, the measured value of the relevant
temperature. The offset register has a default value of 0癈
and has no effect unless the user writes a different value to
it. The resolution of the value in the offset register is
determined by bit 1 of register 0x7C. If the bit is 0 then the
resolution is 0.5癈. If the bit is 1 then the resolution is 1癈.
" Remote1 Offset, register 0x70
" Local Offset, register 0x71
" Remote2 Offset, register 0x72
Push Registers
The NCT7491 allows the user to program 4 temperatures
into the device that can then be used for fan control and
THERM/SMBALERT functions in the same way as other
temperature sources. These temperatures can be written by
the system SMBus master and should be programmed as 2s
complement values.
" Push0, register 0xC8
" Push1, register 0xC9
" Push2, register 0xCA
" Push3, register 0xCB
Push Limit Registers
There are high, low and THERM limits associated with the
Push channels. The same limits are applied to all 4 channels.
" Push Low Limit register, 0xCF
" Push High limit register, 0xCE
" Push THERM Limit register, 0xD0
Push Tmin/Trange Registers
The Push channels also have associated Tmin/Trange
values for Automatic Fan Control. The hysteresis applied at
the Tmin value can also be programmed.
" Push Tmin, 0xCC
" Push Trange, 0xCD bits <3:0>
" Push Hysteresis, 0xEB bits <3:0>
PECI 3.0 Interface
The PECI 3.0 interface reads thermal data from the up to
4 CPUs located at PECI addresses between 0x30 and 0x37
(the first 4 addresses populated are used), and from 1 or 2
domains per CPU. The hottest reading from the domains for
each CPU is stored in the PECI temperature registers. It can