參數資料
型號： NCT7491RQR2G
廠商： ON Semiconductor
文件頁數： 47/80頁
文件大?。?/td> 844K
描述： IC REMOTE THERMAL MONITOR 24QSOP
標準包裝： 2,500
系列： *
NCT7491
http://onsemi.com
47
Table 37. REGISTER 0x10  Configuration Register 6 (PowerOn Default = 0x18)
Bit
Description
R/W
Mnemonic
<6>
V
CCP
Low
R/W
VCCPLow = 1. When the power is supplied from 3.3 V STANDBY and the core voltage (VCCP)
drops below its VCCP low limit value (Reg. 0x46), the following occurs:
Status Bit 1 in Status Register 1 is set.
SMBALERT
 is generated, if enabled.
PROCHOT
 monitoring is disabled.
Everything is reenabled once VCCP increases above the VCCP low limit.
When VCCP increases above the low limit:
PROCHOT
 monitoring is enabled.
Fans return to their programmed state after a spinup cycle.
<7>
Reserved
R
5.  If an error occurs in the SMBus Master sequence then the interface will attempt to read from the slave device again. The interval between
read attempts is set by SMBRT
Table 38. REGISTER 0x11  Configuration Register 7 (PowerOn Default = 0x04)
Bit
Mnemonic
R/W
Description
<0>
THERMHys
R/W
Setting this bit to 1 enables THERM
 hysteresis. Note that hysteresis on THERM
 is disabled
by default. To enable hysteresis this bit must be set to logic 1 and also bit <2> of register
0x7D must be cleared to 0.
<1>
FSPD
R/W
When set to 1, this bit runs all fans at max speed as programmed in the max PWM duty
cycle registers (0x38 to 0x3A). Poweron default = 0. This bit is not locked at any time.
<2>
Vtt
R/W
Setting this bit to 1 includes Vtt in the analog monitoring cycle
<3>
FSPDIS
R/W
Logic 1 disables fan spinup for two TACH pulses. Instead, the PWM outputs go high for the
entire fan spinup timeout selected.
<4>
TODIS
R/W
When this bit is set to 1, the SMBus timeout feature is disabled.
In this state, if at any point during an SMBus transaction involving the NCT7491 activity
ceases for more than 35 ms, the NCT7491 assumes the bus is locked and releases the bus.
This allows the NCT7491 to be used with SMBus controllers that cannot handle SMBus
timeouts. (Lockable.)
<5>
SMBFS1
R/W
PWM1 response to 3 consecutive SMBus Slave device errors; 0=no response; 1=PWM1 go
to max speed or 100%
<6>
SMBFS2
R/W
PWM2 response to 3 consecutive SMBus Slave device errors; 0=no response; 1=PWM2 go
to max speed or 100%
<7>
SMBFS3
R/W
PWM3 response to 3 consecutive SMBus Slave device errors; 0=no response; 1=PWM3 go
to max speed or 100%
Table 39. REGISTER 0x12  Interrupt Status 6 (PowerOn Default = 0x00)
Bit
Mnemonic
R/W
Description
<0>
OOL0
R
1 = ALERT assertion in register 0x41
<1>
OOL4
R
1 = ALERT assertion in register 0x7E
<2>
OOL5
R
1 = ALERT assertion in register 0xB6
<3>
OOL6
R
1 = ALERT assertion in register 0xB7
<4>
OOL7
R
1 = ALERT assertion in register 0xB8
<5>
OOL8
R
1 = ALERT assertion in register 0xB9
<6>
OOL9
R
1 = ALERT assertion in register 0xBA
<7>
OOL10
R
1 = ALERT assertion in register 0x89
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