NCT7491
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TACH Measurement Overview
The fan counter does not count the fan TACH output
pulses directly because the fan speed could be less than 1000
RPM, and it takes several seconds to accumulate a
reasonably large and accurate count. Instead, the period of
the fan revolution is measured by gating an onchip 78 kHz
oscillator into the input of a 16bit counter for N periods of
the fan TACH output (see Figure 21) so the accumulated
count is actually proportional to the fan tachometer period
and inversely proportional to the fan speed. N, the number
of pulses counted, is determined by the settings of the TACH
pulses per revolution register (0x7B). This register contains
two bits for each fan, allowing one, two (default), three, or
four TACH pulses to be counted.
Figure 21. Fan Speed Measurement
Fan Speed Measurement Registers
The fan tachometer registers are 16bit values consisting
of a 2byte read from the NCT7491.
" Register 0x28, TACH1 Low Byte
" Register 0x29, TACH1 High Byte
" Register 0x2A, TACH2 Low Byte
" Register 0x2B, TACH2 High Byte
" Register 0x2C, TACH3 Low Byte
" Register 0x2D, TACH3 High Byte
" Register 0x2E, TACH4 Low Byte
" Register 0x2F, TACH4 High Byte
Reading Fan Speed from the NCT7491
The measurement of fan speeds involves a 2register read
for each measurement. The low byte should be read first.
This causes the high byte to be frozen until both high and low
byte registers have been read, preventing erroneous TACH
readings. The fan tachometer reading registers report back
the number of 12.82 us period clocks (78 kHz oscillator)
gated to the fan speed counter, from the rising edge of the
first fan TACH pulse to the rising edge of the third fan TACH
pulse (assuming two pulses per revolution are being
counted). Because the device is essentially measuring the
fan TACH period, the higher the count value, the slower the
fan is actually running. A 16bit fan tachometer reading of
0xFFFF indicates that either the fan has stalled or is running
very slowly (<100 RPM).
Because the actual fan TACH period is being measured,
falling below a fan TACH limit by 1 sets the appropriate
status bit and can be used to generate an SMBALERT
Fan TACH Limit Registers
The fan TACH limit registers are 16bit values consisting
of two bytes.
" Register 0x54, TACH1 Minimum Low Byte = 0xFF
default
" Register 0x55, TACH1 Minimum High Byte = 0xFF
default
" Register 0x56, TACH2 Minimum Low Byte = 0xFF
default
" Register 0x57, TACH2 Minimum High Byte = 0xFF
default
" Register 0x58, TACH3 Minimum Low Byte = 0xFF
default
" Register 0x59, TACH3 Minimum High Byte = 0xFF
default
" Register 0x5A, TACH4 Minimum Low Byte = 0xFF
default
" Register 0x5B, TACH4 Minimum High Byte = 0xFF
default
Fan Speed Measurement Rate
The fan TACH readings are normally updated once every
second. When set, the FAST bit (Bit 3) of Configuration
Register 3 (0x78), updates the fan TACH readings every
250 ms.
DC Bits
If any of the fans are not being driven by a PWM channel
but are powered directly from 5.0 V or 12 V, their associated
dc bit in Configuration Register 3 (0x78) should be set. This