NCT7491
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18
PECI Limits:
" PECI Low Limit, 0x34
" PECI High Limit, 0x35
These registers are used to set the allowable PECI
temperature range. If the temperature is above the high limit
or below the low limit then a status bit is set and pins
configured as SMBALERT will assert. The high and low
limit values are common to all PECI channels. The format
depends on whether Absolute PECI mode is enabled. If it is
then the limits are in unsigned format. If Absolute PECI
mode is not enabled then the format is 2s complement.
PECI T
CONTROL
Values:
" PECI0 T
CONTROL
, 0x3D
" PECI1 T
CONTROL
, 0x08
" PECI2 T
CONTROL
, 0x09
" PECI3 T
CONTROL
, 0x0A
These values set the failsafe fan assertion temperature.
The response of the fans is determined by the THERM
configuration registers and is described in the THERM
Assertion section of this document. These values can be
read from the CPU via the PECI interface or programmed
directly by the user.
The format depends on whether Absolute PECI mode is
enabled. If it is then the limit is in unsigned format. If
Absolute PECI mode is not enabled then the format is 2s
complement.
PECI T
JMAX
Values:
" PECI0 T
JMAX
, 0x0B
" PECI1 T
JMAX
, 0x0C
" PECI2 T
JMAX
, 0x0D
" PECI3 T
JMAX
, 0x0E
Each CPU has a maximum junction temperature T
JMAX
.
These values for the populated CPUs are read via the PECI
3.0 interface by the NCT7491. They can also be
overwritten by the user. They are used to determine the
absolute PECI temperature. These values are stored as
unsigned data.
PECI Fan Control:
" PECI Tmin, 0x3B
" PECI Trange, 0x3C bits <7:4>
" PWM1 Source1, 0x8A bits <6:3>
" PWM2 Source1, 0x8D bits <6:3>
" PWM3 Source1, 0x90 bits <6:3>
Tmin sets the turnon temperature for any fan that is
controlled by a PECI temperature.
Trange sets the range over which the PWM output will
increase from PWMmin to PWMmax.
The PECI Tmin and PECI Trange values are common to
all PECI channels.
The PWMX Source registers are used to assign
temperature control to a fan. The PECI assignment is done
with bits <6:3> in those registers.
The user can choose to use the relative or absolute PECI
temperature values for fan control. If Absolute PECI mode
is used then the maximum valid Tmin value is 175癈.
For full details on the Fan Control implementation see the
Fan Control section of this document
PECI Status Bits:
" PECI0 limit error, 0x43 bit 0
" PECI1 limit error, 0x81 bit 3
" PECI2 limit error, 0x81 bit 4
" PECI3 limit error, 0x81 bit 5
" DATA error, 0x43 bit 1
" COMM error, 0x43 bit 2
" DATA type, 0x43 bits <6:4>
" PECI completion code, 0x81 bit 0
" PECI0 T
CONTROL
exceeded, 0x89 bit 0
" PECI1 T
CONTROL
exceeded, 0x89 bit 1
" PECI2 T
CONTROL
exceeded, 0x89 bit 2
" PECI3 T
CONTROL
exceeded, 0x89 bit 3
The Data Type field indicates the returned code if a DATA
error is generated. Status bits in 0x43 and 0x81 can be
masked by setting the corresponding mask bits in registers
0x82 and 0x83.
Generic PECI Command Block
" CPU Address, 0xD1
" Data Write Length, 0xD2
" Data Read Length, 0xD3
" Data Write Buffer, 0xD4 to 0xE0
" Data Read Buffer, 0xE1 to 0xE9
" Generic PECI Configuration, 0xEA
These registers define the generic PECI interface. An
external master can populate these registers in order to
execute any supported PECI 3.0 commands.
The byte definitions for this block are as follows:
CPU Address sets the target address of the PECI client that
is to be accessed.
Data Write Length sets the number of bytes to be
transferred to the PECI client. This byte should include the
AW FCS byte in its count. The AW FCS byte is
automatically calculated and appended by the NCT7491.
Data Read Length sets the number of bytes to be returned
from the PECI client.
Data Write Buffer is a 13 byte buffer that holds the data to
be transferred to the client. The first byte of this buffer is the
command code that defines the command to be executed.
Data Read Buffer is a 9 byte buffer that will hold the data
returned from the client.