參數(shù)資料
型號: NCT7491RQR2G
廠商: ON Semiconductor
文件頁數(shù): 46/80頁
文件大?。?/td> 844K
描述: IC REMOTE THERMAL MONITOR 24QSOP
標準包裝: 2,500
系列: *
NCT7491
http://onsemi.com
46
Table 35. PECI TJMAX REGISTERS (Note 4) (PowerOn Default = 0x00)
Register Address
R/W
Description
0x0B
R
PECI0 Tjmax
0x0C
R
PECI1 Tjmax
0x0D
R
PECI2 Tjmax
0x0E
R
PECI3 Tjmaxl
4.  The maximum junction temperature for each CPU is returned in these registers. These are automatically read from the PECI interface on
powerup
Table 36. REGISTER 0x0F  PECI Configuration Register 4 (PowerOn Default = 0x00)
Bit
Mnemonic
R/W
Description
<1:0>
DM0CPU
R/W
Sets the DIMM0 CPU assignment:
00 = CPU0
01 = CPU1
10 = CPU2
11 = CPU3
<3:2>
DM1CPU
R/W
Sets the DIMM1 CPU assignment:
00 = CPU0
01 = CPU1
10 = CPU2
11 = CPU3
<5:4>
DM2CPU
R/W
Sets the DIMM2 CPU assignment:
00 = CPU0
01 = CPU1
10 = CPU2
11 = CPU3
<7:6>
DM3CPU
R/W
Sets the DIMM3 CPU assignment:
00 = CPU0
01 = CPU1
10 = CPU2
11 = CPU3
Table 37. REGISTER 0x10  Configuration Register 6 (PowerOn Default = 0x18)
Bit
Mnemonic
R/W
Description
<0>
PWM1Mode
R/W
0 = PWM1 uses Tmin/Trange control
1 = PWM1 uses LUT control
<1>
PWM2Mode
R/W
0 = PWM 2 uses Tmin/Trange control
1 = PWM2 uses LUT control
<2>
PWM3Mode
R/W
0 = PWM3 uses Tmin/Trange control
1 = PWM3 uses LUT control
<4:3>
SMBRT
(Note 5)
R/W
Sets the SMBus Master Retry delay time:
00 = 1 ms
01 = 2 ms
10 = 4 ms
11 = 8 ms
<5>
IFT
R/W
1 = Ignore first tach pulse during tach measurement. This can be used to stabilize readings from
fans that produce erroneous glitches in 3wire mode.
5.  If an error occurs in the SMBus Master sequence then the interface will attempt to read from the slave device again. The interval between
read attempts is set by SMBRT
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