參數(shù)資料
型號(hào)： P89LPC9402FBD,557
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 18/60頁(yè)
文件大?。?/td> 0K
描述： IC 80C51 MCU FLASH 8K 64-LQFP
標(biāo)準(zhǔn)包裝： 450
系列： LPC900
核心處理器： 8051
芯體尺寸： 8-位
速度： 18MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，LCD，LED，POR，PWM，WDT
輸入/輸出數(shù)： 23
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.4 V ~ 3.6 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-LQFP
包裝： 托盤(pán)
其它名稱： 935288631557
P89LPC9402_1
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 22 April 2009
25 of 60
NXP Semiconductors
P89LPC9402
8-bit microcontroller with accelerated two-clock 80C51 core
7.15.2 Power-on detection
The Power-on detect has a function similar to the brownout detect, but is designed to work
as power comes up initially, before the power supply voltage reaches a level where
brownout detect can work. The POF ag in the RSTSRC register is set to indicate an
initial power-up condition. The POF ag will remain set until cleared by software.
7.16 Power reduction modes
The P89LPC9402 supports three different power reduction modes. These modes are Idle
mode, Power-down mode, and total Power-down mode.
7.16.1 Idle mode
Idle mode leaves peripherals running in order to allow them to activate the processor
when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle
mode.
7.16.2 Power-down mode
The Power-down mode stops the oscillator in order to minimize power consumption. The
P89LPC9402 exits Power-down mode via any reset, or certain interrupts. In Power-down
mode, the power supply voltage may be reduced to the data retention voltage VDDR. This
retains the RAM contents at the point where Power-down mode was entered. SFR
contents are not guaranteed after VDD has been lowered to VDDR, therefore it is highly
recommended to wake-up the processor via reset in this case. VDD must be raised to
within the operating range before the Power-down mode is exited.
Some chip functions continue to operate and draw power during Power-down mode,
increasing the total power used during power-down. These include: Brownout detect,
watchdog timer, Comparators (note that Comparators can be powered-down separately),
and RTC/System Timer. The internal RC oscillator is disabled unless both the RC
oscillator has been selected as the system clock and the RTC is enabled.
7.16.3 Total Power-down mode
This is the same as Power-down mode except that the brownout detection circuitry and
the voltage comparators are also disabled to conserve additional power. The internal RC
oscillator is disabled unless both the RC oscillator has been selected as the system clock
and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during
power-down, there will be high power consumption. Please use an external low frequency
clock to achieve low power with the RTC running during power-down.
7.17 Reset
The P1.5/RST pin can function as either a LOW-active reset input or as a digital input,
P1.5. The Reset Pin Enable (RPE) bit in UCFG1, when set to logic 1, enables the external
reset input function on P1.5. When cleared, P1.5 may be used as an input pin.
Remark: During a power-up sequence, the RPE selection is overridden and this pin
always functions as a reset input. An external circuit connected to this pin should not
hold this pin LOW during a power-on sequence as this will keep the device in reset.
After power-up this pin will function as dened by the RPE bit. Only a power-up reset will
temporarily override the selection dened by RPE bit. Other sources of reset will not
override the RPE bit.
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